Interconnection Structure And Method For Semiconductor Device

• US 20140264873A1
• Filed: 07/08/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ting, Chih-Yuan, Wu, Chung-Wen
• Granted Patent: US 9,076,729 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer.

Claims

1. A semiconductor device comprising:

a substrate;

a first dielectric layer disposed over the substrate;

a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer, the metal structure having a shape that includes;

an upper portion with a first width; and

a lower portion with a second width, which is substantially larger than the first width, whereby a notch is formed in the metal structure; and

a second dielectric sub-structure positioned in the notch between the upper portion of the metal structure and the first dielectric layer.

2. The device of claim 1, wherein the sub-structure includes a flat bottom profile.

3. The device of claim 1, wherein the sub-structure includes a non-flat bottom sidewall profile.

4. The device of claim 3, wherein the sub-structure has a deeper portion adjacent a side of the metal structure.

5. The device of claim 3, wherein the sub-structure has a deeper portion on a side of the first dielectric layer.

6. The device of claim 1, wherein the metal structure has a relatively straight sidewall, except where notched by the sub-structure.

7. The device of claim 6, wherein the metal structure is notched on one side by the sub-structure.

8. The device of claim 6, wherein the metal structure is notched on two sides by the sub-structures.

9. The device of claim 1, wherein the upper portion of the first metal structure has a taper sidewall profile, with a top width which is smaller than a bottom width.

10. The device of claim 1, further comprising:

a first barrier layer disposed between the metal structure and the first dielectric layer; and

a second barrier layer disposed between the metal structure and the sub-structure.

11. The device of claim 10, wherein the second barrier layer includes cobalt (Co) deposited selectively on the metal structure.

12. A method for fabricating a semiconductor device, the method comprising:

providing a substrate;

depositing a first dielectric layer over the substrate;

forming a first trench in the first dielectric layer;

filling in the first trench with a first metal layer to form a metal structure with a first width;

forming a notch in the metal structure and the first dielectric layer, wherein the notch defines an upper portion with a second width and a lower portion with the first width of the metal structure, and

filling in the notch with a second dielectric layer.

13. The method of claim 12, wherein the second width of the upper portion of the metal structure is smaller than the first width of the lower portion of the metal structure.

14. The method of claim 12, wherein the notch is formed by etching the metal structure and the first dielectric layer through a patterned first hard mask simultaneously.

15. The method of claim 12, further comprising:

filling in the first trench with a first barrier layer prior to filling in the first metal layer; and

selectively depositing a second barrier layer on the metal structure in the notch, prior to filling in the second dielectric layer.

16. The method of claim 15, wherein the second barrier layer includes cobalt (Co).

17. The method of claim 12, further comprising:

depositing a third dielectric layer over the metal structure;

forming a second trench in the third dielectric layer to expose at least a portion of the upper portion of the metal structure; and

filling in the second trench with a second metal layer.

19. The method of claim 14, further comprising:

filling in the first trench with a first barrier layer prior to filling in the first metal layer;

selectively depositing a second barrier layer on the metal structure in the notch, prior to filling in the second dielectric layer; and

filling in the second trench with a third barrier layer prior to filling in the second metal layer.

20. The method of claim 15, wherein the second barrier layer includes cobalt (Co).

18. A method of forming a structure of a semiconductor device, the method comprising:

providing a substrate;

depositing a first dielectric layer over the substrate;

forming a patterned first hard mask over the first dielectric layer;

etching the first dielectric layer through the patterned first hard mask to form a first trench;

filling in the first trench with a first metal layer to form a metal structure;

forming a patterned second hard mask over the metal structure and the first dielectric layer;

removing a portion of the metal structure and a portion of the first dielectric layer to form a notch, wherein the notch defines an upper portion and lower portion of the metal structure, further wherein a width of the upper portion is smaller than a width of the lower portion;

filling in the notch with a second dielectric layer;

depositing a third dielectric layer over the metal structure;

forming a second trench in the third dielectric layer to expose at least a portion of the upper portion of the metal structure; and

filling in the second trench with a second metal layer.