STUBBY PADS FOR CHANNEL CROSS-TALK REDUCTION

• US 20140264907A1
• Filed: 03/13/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Kemal Aygun, Nevin Altunyurt, Tolga Memioglu
• Inventors: AYGUN, Kemal, ALTUNYURT, Nevin, MEMIOGLU, Tolga
• Granted Patent: US 9,105,635 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2223/6633 Transition between different waveguide types
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/16267 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 μm) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 μm), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.

Claims

1. An integrated circuit (IC) package substrate, comprising:

a first conductive vertical transition passing through a thickness of the substrate beginning at a first top-side metal feature on a first substrate side and ending at a first bottom-side metal feature on a second substrate side, opposite the first side; and

a second conductive vertical transition passing through the substrate thickness beginning at a second top-side metal feature on the first substrate side and ending at a second bottom-side metal feature on the second substrate side, wherein the perimeters of first and second bottom-side metal features include complementary capacitive coupling stubs.

2. The IC package substrate of claim 1, wherein the capacitive coupling stubs comprise a first stub on the first bottom-side metal feature having edges interdigitated with a pair of second stubs on the second bottom-side metal feature.

3. The IC package substrate of claim 2, wherein the interdigitated edges extend in both a first and second orthogonal dimension with a thickness of the bottom-side metal features in a third dimension, orthogonal to the first and second dimension.

4. The IC package substrate of claim 1, wherein the first and second bottom-side metal features are associated with a first pitch and wherein a capacitive coupling stub on the first bottom-side metal feature is spaced apart from the capacitive coupling stub on the second bottom-side metal feature by a first distance that is less than 10% of the first pitch.

5. The IC package substrate of claim 4, wherein the first and second top-side metal features are associated with a second pitch that is at least an order of magnitude smaller than the first pitch, and are spaced apart by a second distance that is the same order of magnitude as the first distance.

6. The IC package substrate of claim 4, wherein the first distance is between 5 and 50 micrometers (μ

m), wherein the first pitch is between 20 and 50 mils, and wherein the first and second bottom-side metal features have a thickness of 5-30 μ

m.

7. The IC package substrate of claim 1, where the first and second transitions are a pair of transitions within a greater plurality of transitions, and each of the greater plurality of transitions include metal features on a surface of the substrate that have capacitive coupling stubs.

8. The IC package substrate of claim 7, wherein the capacitive coupling stubs comprise a first stub on the first bottom-side metal feature having an edge adjacent to an edge of a second stub on the second bottom-side metal feature;

and

wherein the plurality of transitions further includes a third bottom-side metal feature on the second substrate side, the third bottom-side metal feature including a capacitive coupling stub adjacent to a third stub on the second bottom side metal feature.

9. The IC package substrate of claim 8, wherein the plurality of transitions further includes a fourth bottom-side metal feature on the second substrate side, the fourth bottom-side metal feature including a capacitive coupling stub adjacent to a fourth stub on the third bottom-side metal feature and a capacitive coupling stub adjacent to fifth stub on the first bottom-side metal feature.

10. The IC package substrate of claim 8, wherein the greater plurality of transitions further includes a conductive vertical transition spaced farther away from the first transition than is the second transition, and terminating with a metal feature lacking any capacitive coupling stubs.

13. A computing platform, comprising:

the IC package substrate of claim 1; and

an integrated circuit (IC) including a first signal I/O connected to the first top-side metal feature and a second signal I/O connected to the second top-side metal feature.

14. The computing platform of claim 13, further comprising an interposer or printed circuit board (PCB) physically connected to the first and second bottom-side metal features with complementary socket features having approximately a same pitch as that of the first and second bottom-side metal features.

15. The computing platform of claim 14, wherein the first and second bottom-side metal features comprise two pads in a land grid array (LGA), wherein the complementary socket features comprise pins extending from a PCB, and wherein the PCB electrically connects the first and second signal I/O to separate channels of a dynamic random access memory (DRAM) socket.

16. The computing platform of claim 15, wherein the first and second bottom-side metal features comprise two pins in a pin grid array (PGA), wherein the complementary socket features comprise lands disposed on a PCB, and wherein the PCB electrically connects the first and second signal I/O to separate channels of a dynamic random access memory (DRAM) socket.

11. An integrated circuit (IC) package substrate, comprising:

a plurality of signal lines adjacent to one another and extending through a thickness of the substrate; and

one or more ground line adjacent to at least one of the plurality of signal lines and extending through the thickness of the substrate;

wherein each of the plurality of signal lines terminate at surface pads that include capacitive coupling stubs interdigitated with stubs of at least one other adjacent pad, and wherein the ground line terminates at a surface pad that has no capacitive coupling stubs.

12. The IC package substrate of claim 11, wherein the first and second bottom-side metal features are associated with a first pitch and wherein the capacitive coupling stubs on the first bottom-side metal feature are spaced apart from the capacitive coupling stubs on the second bottom-side metal feature by a first distance that is less than 10% of the first pitch.

17. A computer system comprising:

an integrated circuit (IC) chip comprising at least one logic processor core;

a package substrate; and

an interposer or printed circuit board (PCB), wherein the package substrate comprises;

a first conductive vertical transition passing through a thickness of the substrate beginning at a first top-side metal feature connected to the IC chip and ending at a first bottom-side metal feature connected to the interposer or PCB; and

a second conductive vertical transition passing through the substrate thickness beginning at a second top-side metal feature connected to the IC chip and ending at a second bottom-side metal feature connected to the interposer or PCB, wherein the perimeters of first and second bottom-side metal features include capacitive coupling stubs.

18. The system of claim 17, wherein the package substrate is coupled to a PCB through a socket contact, wherein the first and second vertical transitions are to carry crosstalking communication signals to and from the IC that have an aggressor-victim relationship, and wherein the capacitive coupling stubs impart a mutual capacitive coupling between the first and second vertical transitions to reduce the crosstalk.

19. The system of claim 18, wherein the PCB hosts at least one dynamic random-access memory (DRAM), and wherein the crosstalking communication signals are carried by single-ended circuitry coupling the IC to the DRAM.

20. The system of claim 18, wherein the IC chip comprises at least one wireless module, wherein the PCB hosts at balun, and wherein the crosstalking communication signals are carried by differential circuitry coupled to the balun.