INTERLAYER CONDUCTOR AND METHOD FOR FORMING

• US 20140264925A1
• Filed: 04/22/2013
• Published: 09/18/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Granted Patent: US 8,928,149 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y₁ that is nominally equal to the transverse dimension of the contact area opening, and the second portion having a transverse dimension Y₂ that is greater than the transverse dimension of the contact area opening. The active layers can be bit lines or word lines for a 3-D memory device, or other active layers in integrated circuits.

Claims

1. A method for forming a device having contact landing areas at varying depths in a substrate, comprising:

forming a patterned, first mask layer on the substrate, including a contact area opening on the substrate;

forming a second mask layer over the first mask layer, the second mask layer filling said contact area opening;

using a patterned, third mask layer to define a starting via location within the contact area opening;

etching a via through the second mask layer at the starting via location; and

forming contact landing areas at a plurality of depths in the substrate by iteratively etching an increment in depth into the substrate through the via, and trimming the second mask layer to enlarge the via.

2. The method of claim 1, wherein the contact area opening has a longitudinal dimension and a transverse dimension, and including forming interlayer conductors having a first portion within the contact area opening through the first mask layer and extending to a corresponding one of said contact landing areas, and a second portion above the first mask layer,

said first portion having a transverse dimension Y₁ that is nominally equal to the transverse dimension of the contact area opening, and

said second portion having a transverse dimension Y₂ that is greater than the transverse dimension of the contact area opening.

3. The method of claim 1, including

forming an insulating layer, the insulating layer filling the contact area opening and having a depth over the substrate outside the contact area opening;

using a patterned conductor mask, etching through the insulating layer at interlayer conductor locations to the contact landing areas at the plurality of depths to form interlayer conductor vias; and

filling the interlayer conductor vias with a conductive material to form interlayer conductors.

4. The method of claim 3, wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L;

and

each interlayer conductor has a longitudinal dimension X_V and a transverse dimension Y_V, where X_V is less than the average longitudinal pitch of the contact landing areas, X_V is less than Y_V, and Y_V is greater than Y_L.

5. The method of claim 3, wherein the contact landing areas have longitudinal pitches, and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L;

and

the interlayer conductors have a first portion within the contact area opening below the first mask layer, and a second portion in the first mask layer in part outside the contact area opening, the first portion having a first longitudinal dimension X₁ and a first transverse dimension Y₁, and the second portion having a second longitudinal dimension X₂ and a second transverse dimension Y₂,

wherein X₁ is less than the longitudinal pitch of a corresponding landing area for the interlayer conductor, Y₁ is nominally equal to Y_L, and Y₂ is greater than Y_L.

6. The method of claim 1, wherein said substrate comprises a stack including a plurality of active layers separated by insulating layers, and said contact landing areas are on active layers in the plurality of active layers.

7. A method for forming a device having contact landing areas at varying depths in a substrate, comprising:

forming contact landing areas at a plurality of depths in the substrate within a contact area opening in a first insulating layer, wherein the contact area opening has a longitudinal dimension and a transverse dimension;

forming an etch stop layer (e.g., silicon nitride) over the contact landing areas on substrate, on sidewalls of the contact area opening, and on the overlying mask layer;

forming a second insulating layer over the etch stop layer, the insulating layer filling the contact area opening;

defining a plurality of interlayer conductor locations for corresponding contact landing areas in the contact area opening, the interlayer conductor locations having a transverse dimension that is greater than the transverse dimension of the contact area opening, and having a longitudinal dimension;

etching through the second insulating layer at the interlayer conductor locations by using a process selective for the second insulating layer over the etch stop layer, and then etching openings in the etch stop layer exposing the contact landing areas at the plurality of depths to form interlayer conductor vias while leaving at least portions of the etch stop layer on the sidewalls; and

filling the interlayer conductor vias with a conductive material to form interlayer conductors.

8. The method of claim 7, said interlayer conductors having a first portion within the contact area opening through the first mask layer and extending to a corresponding one of said contact landing areas, and a second portion above the first mask layer,

said first portion having a transverse dimension Y₁ that is nominally equal to the transverse dimension of the contact area opening, and

said second portion having a transverse dimension Y₂ that is greater than the transverse dimension of the contact area opening.

9. The method of claim 7, wherein said forming contact landing areas includes:

forming a second mask layer (e.g. spin coated ODL) over the first insulating layer, the second mask layer filling said contact area opening;

etching a via through the second mask layer at a starting via location; and

iteratively etching an increment in depth into the substrate through the via, and trimming the second mask layer to enlarge the via.

10. The method of claim 7, wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L;

and

each interlayer conductor has a longitudinal dimension X_V and a transverse dimension Y_V, where X_V is less than the average longitudinal pitch of the contact landing areas, X_V is less than Y_V, and Y_V is greater than Y_L.

11. The method of claim 7, wherein the contact landing areas have longitudinal pitches, and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L;

and

the interlayer conductors have a first portion within the contact area opening below the first insulating layer, and a second portion in the first insulating layer in part outside the contact area opening, the first portion having a first longitudinal dimension X₁ and a first transverse dimension Y₁, and the second portion having a second longitudinal dimension X₂ and a second transverse dimension Y₂,

wherein X₁ is less than the longitudinal pitch of a corresponding landing area for the interlayer conductor, Y₁ is nominally equal to Y_L, and Y₂ is greater than Y_L.

12. The method of claim 7, wherein said substrate comprises a stack including a plurality of active layers separated by insulating layers, and said contact landing areas are on active layers in the plurality of active layers.

13. A 3-D structure, comprising:

a stack including a plurality of active layers at a corresponding plurality of depths in the stack, including a top active layer, and a plurality of contact landing areas on respective active layers;

a first insulating layer over the top active layer, and having a contact area opening over the plurality of contact landing areas, the contact area opening having a longitudinal dimension and a transverse dimension;

a second insulating layer over the first insulating layer, and filling the contact area opening and having a depth over the first insulating layer;

a plurality of interlayer conductors in the second insulating layer, the interlayer connectors having a first portion within the contact area opening through the first insulating layer and extending to a corresponding one of said contact landing areas, and a second portion in part outside the contact area opening above the first insulating layer,

said first portion having a transverse dimension Y₁ that is nominally equal to the transverse dimension of the contact area opening, and

said second portion having a transverse dimension Y₂ that is greater than the transverse dimension of the contact area opening.

14. The 3-D structure of claim 13, including a layer of material different than second insulating layer, between on sidewalls of the active layers in the plurality of contact landing areas.

15. The 3-D structure of claim 13, wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L;

and

each interlayer conductor has a longitudinal dimension X_V, where X_V is less than the average longitudinal pitch of the contact landing areas, X_V is less than Y₂, and Y₂ is greater than Y_L.

16. The 3-D structure of claim 13, wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X_L and a transverse dimension Y_L, where X_L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y_L is less than X_L.

17. The 3-D structure of claim 13, wherein the first portion has a first longitudinal dimension X₁ and the second portion has a second longitudinal dimension X₂, and the first longitudinal dimension X₁ and the second longitudinal dimension X₂ are nominally equal.

18. The 3-D structure of claim 13, including a patterned conductor layer over the second portions of the plurality of interlayer conductors, and interlayer contacts between said second portions and the patterned conductor layer, at least some of said interlayer contacts being disposed over the contact area opening.

19. The 3-D structure of claim 13, wherein said second portions of the plurality of interlayer conductors comprise patterned conductor lines having interlayer contacts to other elements outside of the contact area opening.

20. The 3-D structure of claim 13, wherein said plurality of active layers comprise capacitor plates.

21. The 3-D structure of claim 13, wherein said plurality of active layers comprise integrated circuits in a multichip package.