INTERLAYER CONDUCTOR STRUCTURE AND METHOD

• US 20140264934A1
• Filed: 10/03/2013
• Published: 09/18/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Granted Patent: US 8,993,429 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.

Claims

1. A method of forming an interconnect conductor structure, comprising:

forming a stack of pads coupled to respective active layers of a circuit;

forming interlayer conductors arranged in rows extending in an X direction in contact with landing areas on corresponding pads in the stack, adjacent rows being separated from one another in a Y direction generally perpendicular to the X direction, the interlayer conductors in a row having a first pitch in the X direction, and the interlayer conductors in adjacent rows being offset in the X direction by an amount less than the first pitch; and

forming interconnect conductors over and in contact with interlayer conductors, the interconnect conductors extending in the Y direction and having a second pitch less than the first pitch.

2. The method of claim 1, including forming N rows of openings for the interlayer conductors in the stack of pads, where N is an integer greater than 2.

3. The method of claim 1, wherein the X direction is parallel to the first side.

4. The method of claim 1, wherein the interlayer conductors forming step further comprises:

forming rows of via openings in the stack of pads to expose landing areas on the active layers so that the landing areas in a row are partially offset in the Y direction relative to landing areas in an adjacent row;

filling the via openings with an insulation material;

forming contact openings in the insulation material in the via openings to expose contact areas on the landing areas; and

forming the interlayer conductors in the contact openings.

5. The method of claim 4, wherein the ICE forming step forms the ICEs closer to either a left side or a right side of the upper ends of the interlayer conductors in a first row and closer relative to the other side of the upper ends of the interlayer conductors in a second, adjacent row.

6. The method of claim 1, wherein the interconnect conductors extend perpendicular to the first side over the stack of pads.

7. The method of claim 1, wherein said forming the stack of pads includes patterning the active layers to form parallel strips of semiconductor material which terminate in the respective pads, adapted to act as channels of memory cells.

8. The method of claim 1, wherein said forming the stack of pads includes patterning the active layers to form parallel strips of conductive material which terminate in the respective pads, adapted to act as wordlines of memory cells.

9. The method of claim 1, wherein:

the interlayer conductors forming step comprises forming interlayer conductors including lower portions and upper, interlayer conductor extensions (ICEs) extending from upper ends of the lower portions, the ICEs having an ICE width in the X direction, the upper ends of the lower portions having an upper end width in the X direction, the ICE width being less than the upper end width, the ICEs in adjacent rows being offset in the X direction by a lateral offset distance, the lateral offset distance being greater than the ICE width; and

the interconnect conductors are formed over and in contact with the ICEs.

10. A device, comprising:

a stack of pads coupled to respective active layers of a circuit;

interlayer conductors arranged in rows extending in an X direction in contact with landing areas on corresponding pads in the stack;

adjacent rows being separated from one another in a Y direction generally perpendicular to the X direction;

the interlayer conductors in a row having a first pitch in the X direction;

the interlayer conductors in adjacent rows being offset in the X direction by an amount less than the first pitch; and

interconnect conductors over and in contact with interlayer conductors, the interconnect conductors extending in the Y direction and having a second pitch less than the first pitch.

11. The device of claim 10, wherein the interlayer conductors are surrounded by an insulating fill.

12. The device of claim 10, wherein the X direction is parallel to the first side.

13. The device of claim 10, wherein the interconnect conductors extend over the stack of pads and are perpendicular to the first side.

14. The device of claim 10, wherein the interconnect conductors comprise a doped semiconductor material.

15. The device of claim 10, wherein the interconnect conductors comprise a metal material.

16. The device of claim 10, wherein the active layers include parallel strips of semiconductor material which terminate in the respective pads, adapted to act as channels of memory cells.

17. The device of claim 10, wherein the interconnect conductors connect the respective active layers to a decoding circuitry or a read circuitry.

18. The device of claim 10, further comprising:

the interlayer conductors comprising lower portions and upper, interlayer conductor extensions (ICEs) extending from upper ends of the lower portions;

the ICEs having an ICE width in the X direction, the upper ends of the lower portions having an upper end width in the X direction, the ICE width being less than the upper end width;

the ICEs in adjacent rows being offset in the X direction by a lateral offset distance, the lateral offset distance being greater than the ICE width; and

the interconnect conductors being over and in contact with the ICEs.