Interconnect Apparatus and Method

• US 20140264947A1
• Filed: 05/09/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jeng-Shyan, Tsai, Shu-Ting, Yaung, Dun-Nian, Liu, Jen-Cheng, Hung, Feng-Chi, Chou, Shih Pei, Kao, Min-Feng, Chen, Szu-Ying
• Granted Patent: US 9,536,777 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/13056 : Photo transistor
• CPC Class Codes: H01L 2924/1431 : Logic devices

Abstract

A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.

Claims

1. An apparatus comprising:

a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines formed in the first inter-metal dielectric layers over the first substrate;

a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines formed in the second inter-metal dielectric layers over the second substrate; and

a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises;

a first portion formed over a first side of a hard mask layer formed in the first semiconductor chip, wherein the first portion is of a first width, and wherein the first portion of the conductive plug is isolated from the first inter-metal dielectric layers and the second inter-metal dielectric layers by a first dielectric layer; and

a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width, and wherein the second portion of the conductive plug is isolated from the first inter-metal dielectric layers by a second dielectric layer.

2. The apparatus of claim 1, wherein:

the hard mask layer is formed by the first metal lines.

3. The apparatus of claim 1, wherein:

the hard mask layer is formed by redistribution lines of the first semiconductor chip.

4. The apparatus of claim 1, wherein:

the hard mask layer is formed by contacts of the first semiconductor chip.

5. The apparatus of claim 1, wherein:

the first portion is in a first trench located between the first metal lines and the second metal lines, and wherein the first dielectric layer is formed along sidewalls of the first trench; and

the second portion is in a second trench located between the first metal lines and a backside of the first substrate, and wherein the second dielectric layer is formed along sidewalls of the second trench.

6. The apparatus of claim 1, wherein:

the first portion is in a first trench located between contacts of the first semiconductor chip and the second metal lines, and wherein the first dielectric layer is formed along sidewalls of the first trench; and

the second portion is in a second trench located between the contacts of the first semiconductor chip and a backside of the first substrate, and wherein the second dielectric layer is formed along sidewalls of the second trench.

7. The apparatus of claim 1, wherein:

the first portion is in a first trench located between redistribution lines of the first semiconductor chip and the second metal lines, and wherein the first dielectric layer is formed along sidewalls of the first trench; and

the second portion is in a second trench located between the redistribution lines of the first semiconductor chip and a backside of the first substrate, and wherein the second dielectric layer is formed along sidewalls of the second trench.

8. A method comprising:

bonding a first semiconductor chip on a second semiconductor chip, wherein;

the first semiconductor chip comprises a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first interconnect structures formed in the first inter-metal dielectric layers over the first substrate; and

the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second interconnect structures formed in the second inter-metal dielectric layers over the second substrate;

depositing a first hard mask layer over a non-bonding side of the first semiconductor chip;

depositing a second hard mask layer over the first hard mask layer;

etching the first substrate using the second hard mask layer as a first mask;

etching the first inter-metal dielectric layers and the second inter-metal dielectric layers to form a plurality of openings, wherein the first hard mask layer and the first interconnect structures are used as a second mask; and

plating a conductive material in the openings.

9. The method of claim 8, further comprising:

plating the conductive material in the openings to form a conductive plug, wherein;

a first portion of the conductive plug is adjacent to a bonding side of the first semiconductor chip; and

a second portion of the conductive plug is adjacent to the non-bonding side of the first semiconductor chip, and wherein;

the first portion is of a width greater than or equal to a width of a second portion of the conductive plug.

10. The method of claim 8, further comprising:

etching the first inter-metal dielectric layers and the second inter-metal dielectric layers to form the openings, wherein the first hard mask layer and a plurality of first metal lines formed in the first inter-metal dielectric layer are used as the second mask.

11. The method of claim 8, further comprising:

etching the first inter-metal dielectric layers and the second inter-metal dielectric layers to form the openings, wherein the first hard mask layer and a plurality of contacts formed in the first inter-metal dielectric layer are used as the second mask.

12. The method of claim 8, further comprising:

etching the first inter-metal dielectric layers and the second inter-metal dielectric layers to form the openings, wherein the first hard mask layer and a plurality of redistribution lines formed in the first inter-metal dielectric layer are used as the second mask.

13. The method of claim 8, wherein:

the first hard mask layer is formed of poly.

14. The method of claim 8, wherein:

the second hard mask layer is formed of oxide.

15. A method comprising:

bonding a first semiconductor wafer on a second semiconductor wafer, wherein;

the first semiconductor wafer comprises a first substrate, first inter-metal dielectric layers and first interconnect structures formed in the first inter-metal dielectric layers and over the first substrate; and

the second semiconductor wafer comprises a second substrate, second inter-metal dielectric layers and second interconnect structures formed in the second inter-metal dielectric layers and over the second substrate;

depositing a poly layer over a non-bonding side of the first semiconductor wafer;

depositing an oxide layer over the poly layer;

forming a first opening in the first substrate using a first etching process and using the oxide layer as a first hard mask layer;

forming a second opening using a second etching process and using the poly layer and the first interconnect structures as a second hard mask layer, wherein the second opening is formed through the first inter-metal dielectric layers and partially through the second inter-metal dielectric layers; and

plating a conductive material in the first opening and the second opening.

16. The method of claim 15, further comprising:

depositing a bottom anti-reflection coating layer on a backside of the first semiconductor wafer, wherein the bottom anti-reflection coating layer is formed underneath the poly layer.

17. The method of claim 15, further comprising:

forming the second opening using the poly layer and a plurality of metal lines of the first semiconductor wafer as the second hard mask layer.

18. The method of claim 15, further comprising:

forming the second opening using the poly layer and a plurality of contacts of the first semiconductor wafer as the second hard mask layer.

19. The method of claim 15, further comprising:

forming the second opening using the poly layer and a plurality of redistribution lines of the first semiconductor wafer as the second hard mask layer.

20. The method of claim 15, wherein:

the conductive material is copper.