DIGITAL PHASE CONTROLLER FOR TWO-PHASE OPERATION OF A PLASMA REACTOR

• US 20140265910A1
• Filed: 02/06/2014
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kobayashi, Satoru, Ramaswamy, Kartik, Rauf, Shahid, Collins, Kenneth S.
• Granted Patent: US 9,312,106 B2
• Time in Patent Office: Days
• US Class Current: 315/246
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H01J 37/3299 Feedback systems

Abstract

Phase angle between opposing electrodes in a plasma reactor is controlled in accordance with a user selected phase angle. Direct digital synthesis of RF waveforms of different phases for the different electrodes is employed. The synthesis is synchronized with a reference clock. The address generator employed for direct digital synthesis is synchronized with an output clock signal that is generated in phase with the reference clock using a phase lock loop. The phase lock loop operates only during a limited initialization period.

Claims

1. A plasma reactor for processing a workpiece, comprising:

a pair of electrodes coupled to a pair of RF power amplifiers having an RF phase angle between them;

a feedback controller having a phase correction signal output dependent upon said RF phase angle and a user-defined target phase angle;

a clock generator comprising;

(a) an oscillator responsive to a control signal corresponding to a phase difference between said oscillator and a reference clock, and (b) an output clock derived from an output of said oscillator;

an address generator comprising a pair of address outputs incremented in synchronism with said output clock and separated by an address difference dependent upon said phase correction signal output;

a pair of waveform-containing read only memories coupled to receive respective ones of said pair of address outputs, and coupled to respective ones of said RF power amplifiers.

2. The plasma reactor of claim 1 further comprising a microcontroller coupled to said clock generator, said microcontroller adapted to prevent change in said control signal after a limited initialization period.

3. The plasma reactor of claim 2 wherein said microcontroller is coupled to said address generator, said microcontroller further adapted to inactivate said address generator during said limited initialization period.

4. The plasma reactor of claim 2 wherein said feedback controller is comprised in said microcontroller.

5. The plasma reactor of claim 1 wherein said output clock is of a frequency exceeding said reference clock by a first integer multiple, and said oscillator has a frequency exceeding said frequency of said output clock by a second integer multiple.

6. The plasma reactor of claim 5 wherein said first integer multiple is 8 or greater and said second integer multiple is 2 or greater.

7. The plasma reactor of claim 1 wherein said reference clock is on the order of about 60 MHz, said output of said oscillator has a frequency on the order of about 960 MHz, and said output clock is on the order of about 480 MHz.

8. The plasma reactor of claim 1 wherein said phase correction signal output is a function of said RF phase angle and a user-defined target phase angle, and wherein said function comprises a ratio between a frequency of said reference clock and a frequency of said output clock.

9. A plasma reactor for processing a workpiece, comprising:

a pair of electrodes facing a processing zone and a pair of RF power amplifiers coupled to respective ones of said electrodes, there being an RF phase angle between said pair of electrodes;

a feedback controller having a phase correction signal output that is a function of said RF phase angle and a user-defined target phase angle;

a clock generator comprising;

(a) an oscillator responsive to a control signal corresponding to a phase difference between said oscillator and a reference clock, and (b) an output clock derived from an output of said oscillator, said control signal being unchanging following a limited initialization period;

an address generator comprising a pair of address outputs incremented in synchronism with said output clock and separated by an address difference that is a function of said phase correction signal output;

a pair of waveform-containing read only memories coupled to receive respective ones of said pair of address outputs, and coupled to respective ones of said RF power amplifiers.

10. The plasma reactor of claim 9 wherein said address generator is inactive during said limited initialization period.

11. The plasma reactor of claim 9 wherein said function of said phase correction signal comprises a ratio between a frequency of said reference clock and a frequency of said output clock.

12. The plasma reactor of claim 9 wherein said output clock is of a frequency exceeding said reference clock by a first integer multiple, and said oscillator has a frequency exceeding said frequency of said output clock by a second integer multiple.

13. The plasma reactor of claim 12 wherein said first integer multiple is 8 or greater and said second integer multiple is 2 or greater.

14. The plasma reactor of claim 9 wherein said reference clock is on the order of about 60 MHz, said output of said oscillator has a frequency on the order of about 960 MHz, and said output clock is on the order of about 480 MHz.

15. The plasma reactor of claim 9 wherein said address generator comprises a pair of address generators having respective outputs coupled to respective ones of said pair of read only memories.

16. A plasma reactor for processing a workpiece, comprising:

a pair of electrodes facing a processing zone and a pair of RF power amplifiers coupled to respective ones of said electrodes and having an RF phase angle between said pair of electrodes, and a oscillator providing a reference clock directly to one of said pair of RF power amplifiers;

a feedback controller having a phase correction signal output that is a function of said RF phase angle and a user-defined target phase angle;

a clock generator comprising;

(a) an oscillator responsive to a control signal corresponding to a phase difference between said oscillator and a reference clock, and (b) an output clock derived from an output of said oscillator;

an address generator comprising an address output incremented in synchronism with said output clock and having an address that is a function of said phase correction signal output;

a waveform-containing read only memory coupled to receive said address outputs, and coupled to respective ones of said RF power amplifiers.

17. The plasma reactor of claim 16 further comprising a microcontroller coupled to said clock generator, said microcontroller adapted to prevent change in said control signal after a limited initialization period.

18. The plasma reactor of claim 17 wherein said microcontroller is coupled to said address generator, said microcontroller further adapted to inactivate said address generator during said limited initialization period.

19. The plasma reactor of claim 17 wherein said feedback controller is comprised in said microcontroller.

20. The plasma reactor of claim 16 wherein said output clock is of a frequency exceeding said reference clock by a first integer multiple, and said oscillator has a frequency exceeding said frequency of said output clock by a second integer multiple.