Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages

• US 20140266283A1
• Filed: 05/30/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei-Cheng, Hsu, Li-Han, Chiu, Sao-Ling, Hou, Shang-Yun, Jeng, Shin-Puu, Lin, Chen-Hua
• Granted Patent: US 9,581,638 B2
• Time in Patent Office: Days
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/265 Contactless testing of circuits, also in wafer-form G01R31/302
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16113 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1713 Square or rectangular array
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

Claims

1. A method for testing a chip-on-wafer (CoW) structure comprising:

providing a standardized testing structure design for a CoW structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area of a top die in the CoW structure; and

electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

2. The method of claim 1, wherein:

providing the standardized testing structure design further includes placing a probing pad on a peripheral region of a bottom die of the CoW structure and electrically connected to the testing structure; and

electrically testing the plurality of microbumps comprises applying the universal testing probe card to the testing structure through the probing pad.

3. The method of claim 1, wherein placing the testing structure in the pre-selected area of the CoW structure comprises placing the testing structure in a center region of the top die.

4. The method of claim 1, wherein placing the testing structure in the pre-selected area of the CoW structure comprises placing the testing structure in a corner region of the top die.

5. The method of claim 1, further comprising, after electrically testing the plurality of microbumps, physically examining a sample of the plurality of microbumps using an x-ray.

6. The method of claim 1, wherein providing the standardized testing structure design further comprises including a daisy chain in the testing structure.

7. The method of claim 1, wherein providing the standardized testing structure design further comprises including a kelvin structure in the testing structure.

8. The method of claim 1, wherein providing the standardized testing structure design further comprises configuring the testing structure in an L-shape.

9. The method of claim 1, wherein providing the standardized testing structure design further comprises configuring the standardized testing structure design to be included in a variety of top dies of a variety of CoW structures.

10. A method for testing a chip-on-wafer (CoW) structure comprising:

designing, by a processor, a plurality of standardized testing structures for placement in pre-selected regions of a CoW structure and electrically connected to a plurality of probing pads for placement on peripheral regions of a bottom die of the CoW structure; and

electrically testing microbump connections of a plurality of CoW structures, wherein the plurality of CoW structures each include an implementation of the plurality of standardized testing structures electrically connected to the plurality of probing pads.

11. The method of claim 10, wherein electrically testing the microbump connections of the plurality of CoW structures comprises applying a universal testing probe card to the plurality of probing pads electrically connected to the plurality of standardized testing structures in the plurality of CoW structures respectively.

12. The method of claim 10, wherein the pre-selected regions of the CoW structure are corner regions of a plurality of top dies in the CoW structure.

13. The method of claim 10, wherein the pre-selected regions of the CoW structure are center regions of a plurality of top dies in the CoW structure.

14. The method of claim 10 further comprising implementing the plurality of standardized testing structures electrically connected to the plurality of probing pads in the plurality of CoW structures respectively.

15. A chip-on-wafer (CoW) testing mechanism comprising:

a standardized testing structure configured to be placed in a pre-selected region of a top die of a CoW structure; and

a probing pad configured to be placed in a peripheral region of a bottom die of the CoW structure and electronically connected to the standardized testing structure.

16. The CoW testing mechanism of claim 15, wherein the standardized testing structure is further configured to be placed in a variety of top dies of a variety of CoW structures.

17. The CoW testing mechanism of claim 15, wherein the standardized testing structure includes a daisy chain.

18. The CoW testing mechanism of claim 15, wherein the standardized testing structure includes a kelvin structure.

19. The CoW testing mechanism of claim 15, wherein the standardized testing structure has an L-shape.

20. The CoW testing mechanism of claim 15, wherein the top die is an active device die and the bottom die is an interposer wafer.