SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE SAME

• US 20140266364A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Min-Su Kim, Rahul Singh
• Inventors: SINGH, Rahul, KIM, Min-Su
• Granted Patent: US 9,160,317 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence

Abstract

Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses.

Claims

1. A semiconductor circuit comprising:

a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse;

a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse;

a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses; and

a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on the data values of the input signal and the first and second read pulses.

2. The semiconductor circuit of claim 1, wherein the first read pulse and the second read pulse have different pulse widths.

3. The semiconductor circuit of claim 2, further comprising an input buffer circuit that is configured to invert the input signal, wherein:

when a data value of the input signal is a first data value, and an inverted data value of the input signal is a second data value, the pulse width of the first read pulse is smaller than that of the second read pulse; and

when a data value of the input signal is the second data value, and the inverted data value of the input signal is the first data value, the pulse width of the first read pulse is larger than that of the second read pulse.

4. The semiconductor circuit of claim 3, wherein the first data value has a data value of 1, and the second data value has a data value of 0.

5. The semiconductor circuit of claim 1, wherein the first read pulse generated by the first pulse generating circuit has a first level, and the second read pulse generated by the second pulse generating circuit has a second level different from the first level.

6. The semiconductor circuit of claim 5, wherein the first level includes a logical high level and the second level includes a logical low level.

7. The semiconductor circuit of claim 1, wherein one of the first dynamic node and the second dynamic node is pre-charged before a rising edge of the clock signal is generated, and the other is pre-discharged before the rising edge of the clock signal is generated.

8. The semiconductor circuit of claim 7, wherein the first dynamic node is pre-charged before the rising edge of the clock signal is generated, and the second dynamic node is pre-discharged before the rising edge of the clock signal is generated.

9. The semiconductor circuit of claim 1, further comprising an input buffer circuit that is configured to invert the input signal, wherein:

when a data value of the input signal is a first data value, and an inverted data value of the input signal is a second data value, the dynamic pull-up stage is configured to pull up a voltage level of the second dynamic node; and

when a data value of the input signal is the second data value, and an inverted data value of the input signal is the first data value, the dynamic pull-down stage is configured to pull down a voltage level of the first dynamic node.

10. The semiconductor circuit of claim 9, wherein the first data value has a data value of 1, and the second data value has a data value of 0.

11. The semiconductor circuit of claim 1, further comprising an input buffer circuit that is configured to adjust a slope of the rising edge or falling edge of the input signal by gain control.

12. The semiconductor circuit of claim 1, further comprising a push-pull stage that is configured to develop a voltage level of a static node based at least on the voltage levels of the first and second dynamic nodes.

13. The semiconductor circuit of claim 12, wherein:

the push-pull stage includes a first transistor gated by the voltage level of the first dynamic node;

the first transistor of the push-pull stage is configured to pull up the voltage level of the static node;

the push-pull stage further includes a second transistor gated by the voltage level of the second dynamic node; and

the second transistor of the push-pull stage is configured to pull down the voltage level of the static node.

14. The semiconductor circuit of claim 13, wherein the first transistor includes a PMOS transistor and the second transistor includes an NMOS transistor.

15. The semiconductor circuit of claim 12, further comprising a keeper stage that is configured to maintain the voltage level of the static node.

16. The semiconductor circuit of claim 15, wherein:

the keeper stage includes a first transistor gated by the voltage level of the first dynamic node;

the first transistor of the keeper stage is configured to maintain the voltage level of the static node;

the keeper stage further includes a second transistor gated by the voltage level of the second dynamic node; and

the second transistor of the keeper stage is configured to maintain the voltage level of the static node.

17. The semiconductor circuit of claim 15, wherein the keeper stage includes an inverter configured to be controlled by the clock signal and to maintain the voltage level of the static node.

18. The semiconductor circuit of claim 1, comprising a flip-flop circuit.

19. A semiconductor circuit comprising:

a dynamic stage enabled to a rising edge of a clock signal, and configured to generate first and second read pulses independent of each other, and to develop a voltage level of one of first or second dynamic nodes based at least on data values of an input signal and the generated first and second read pulses; and

a push-pull stage configured to read a data value of the input signal by developing a voltage level of a static node based at least on the voltage levels of the input signal and the generated first and second read pulses.

20. The semiconductor circuit of claim 19, wherein a pulse width of the first read pulse when a data value of the input signal is a first data value is different from a pulse width of the second read pulse when a data value of the input signal is a second data value.

21. The semiconductor circuit of claim 20, wherein a pulse width of the second read pulse when a data value of the input signal is the first data value is different from a pulse width of the second read pulse when a data value of the input signal is the second data value.

22. The semiconductor circuit of claim 21, wherein:

a pulse width of the first read pulse when a data value of the input signal is the first data value is smaller than a pulse width of the first read pulse when the data value of the input signal is the second data value; and

a pulse width of the second read pulse when a data value of the input signal is the first data value is larger than a pulse width of the second read pulse when the data value of the input signal is the second data value.

23. The semiconductor circuit of claim 19, wherein the first dynamic node is configured to be pre-charged before the rising edge of the clock signal is generated, and the second dynamic node is configured to be pre-discharged before the rising edge of the clock signal is generated.

24. The semiconductor circuit of claim 23, wherein when the data value of the input signal is a first data value, the dynamic stage is configured to pull up the voltage level of the second dynamic node, and when the data value of the input signal is a second data value, the dynamic stage is configured to pull down the voltage level of the first dynamic node.

25. A method of operating a semiconductor circuit, the method comprising:

independently generating first and second read pulses enabled to a rising edge of a clock signal; and

reading a data value of an input signal by pulling down a first dynamic node or pulling up a second dynamic node based at least on the voltage levels of the input signal and the independently generated first and second read pulses.

26. The method of claim 25, wherein the first read pulse and the second read pulse have different pulse widths.

27. The method of claim 25, wherein a pulse width of the first read pulse when a data value of the input signal is a first data value is different from a pulse width of the first read pulse when a data value of the input signal is a second data value.

28. The method of claim 27, wherein a pulse width of the second read pulse when a data value of the input signal is the first data value is different from a pulse width of the second read pulse when a data value of the input signal is the second data value.

29. A system, comprising:

a processor coupled to a bus; and

a memory coupled to the bus and to the processor,

wherein at least one of the processor or the memory comprises a semiconductor flip-flop circuit having a first inverting stage, a pulse-based dynamic stage, a push-pull stage, and a second inverting stage,

wherein the pulse-based dynamic stage comprises pulse generators configured to generate at least two read pulses independent from each other.

30. The system of claim 29, wherein the first inverting stage includes an input buffer circuit that is configured to adjust a slope of the rising edge or falling edge of an input signal by gain control.

31. The system of claim 29, wherein the pulse-based dynamic stage includes a first pulse generator, a dynamic pull-up stage, a second pulse generator, and a dynamic pull-down stage.

32. The system of claim 31, wherein:

the dynamic pull-up stage is configured to pull up a voltage level of a pre-discharged dynamic node responsive to a pulse generated by at least one of the first pulse generator or the second pulse generator; and

the dynamic pull-down stage is configured to pull down a voltage level of a precharged dynamic node responsive to a pulse generated by at least one of the first pulse generator or the second pulse generator.

33. The system of claim 32, wherein the push-pull stage includes:

a first transistor connected to the pre-discharged dynamic node;

a second transistor connected to the precharged dynamic node; and

a static node connected to the first and second transistors.

34. The system of claim 33, wherein the static node is connected to the second inverting stage.