Scalable Periphery Tunable Matching Power Amplifier

• US 20140266460A1
• Filed: 03/12/2013
• Published: 09/18/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Nobbe, Dan William, Halchin, David, Dykstra, Jeffrey A., Kovac, David, Kaatz, Gary Frederick, Olson, Chris, Gaynor, Michael P., Mekechuk, Kelly Michael
• Granted Patent: US 9,294,056 B2
• Time in Patent Office: Days
• US Class Current: 330/295
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21109 An input signal being distributed by switching to a plurality of paralleled power amplifiers
• CPC Class Codes: H03F 2203/7215 the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Claims

1. An amplifier, comprising:

a scalable periphery amplifier comprising one or more unit cells connected in parallel with each other and adapted to be selectively activated or deactivated, wherein each unit cell comprises a plurality of active devices configured to operate as an amplifier;

an output tunable matching network operatively connected to an output of the scalable periphery amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the scalable periphery amplifier; and

an amplifier control circuitry configured to selectively activate or deactivate the one or more unit cells, thus varying a total output power from the amplifier,

wherein the plurality of active devices of the one or more unit cells are a stack of a plurality of transistors, an input transistor of the plurality of transistors in the stack being configured to receive an input signal of the scalable periphery amplifier.

2. The amplifier according to claim 1, wherein the plurality of transistors of the stack are configured to substantially equalize an output voltage at an output terminal of the stack across the plurality of transistors of the stack.

3. The amplifier according to claim 2, further comprising an input tunable matching network operatively connected to an input of the scalable periphery amplifier, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the scalable periphery amplifier.

4. The amplifier according to claim 2, wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

5. The amplifier according to claim 3, wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

6. The amplifier according to any one of claims 2, 3, 4 or 5, wherein the output tunable matching network is configured to be adjusted to switch an operation of the scalable periphery amplifier between two or more classes of amplifier operation.

7. The amplifier according to claim 6, wherein the output tunable matching network is configured to affect a harmonic termination of the amplifier according to a desired class of amplifier operation.

8. The amplifier according to any one of claims 2, 3, 4 or 5, wherein the amplifier control circuitry is configured to switch an operation of one or more of the unit cells between two or more classes of amplifier operation.

9. The amplifier according to any one of claims 2, 3, 4 or 5, wherein the amplifier control circuitry is configured to select a first class of amplifier operation in correspondence to a first group of unit cells and a second class of amplifier operation in correspondence to a second group of unit cells, wherein the first group of unit cells and the second group of unit cells comprise one or more unit cells from the one or more unit cells.

10. The amplifier according to any one of claims 2, 3, 4 or 5, wherein one or more of:

a) the amplifier control circuitry, and b) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

11. The amplifier according to claim 3 or claim 5, wherein one or more of:

a) the amplifier control circuitry, b) the input tunable matching network, and c) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

12. The amplifier according to claim 4 or claim 5, wherein one or more of:

a) the amplifier control circuitry, b) the output tunable matching network, and c) the bias applied to the one or more unit cells, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

13. The amplifier according to claim 5, wherein one or more of:

a) the amplifier control circuitry, b) the input tunable matching network, c) the bias applied to the one or more unit cells, and d) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence to an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

14. The amplifier according to claim 10, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

15. The amplifier according to claim 11, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

16. The amplifier according to claim 12, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

17. The amplifier according to claim 13, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

18. The amplifier according to claim 14, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

19. The amplifier according to claim 18, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

20. The amplifier according to claim 19, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

21. The amplifier according to claim 18, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

22. The amplifier according to claim 15, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

23. The amplifier according to claim 22, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

24. The amplifier according to claim 23, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

25. The amplifier according to claim 22, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

26. The amplifier according to claim 16, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

27. The amplifier according to claim 26, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

28. The amplifier according to claim 27, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

29. The amplifier according to claim 26, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

30. The amplifier according to claim 17, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

31. The amplifier according to claim 30, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

32. The amplifier according to claim 31, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

33. The amplifier according to claim 30, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

34. The amplifier according to claim 1, wherein the stack of a plurality of transistors is a stack of at least three transistors.

35. The amplifier according to claim 34, further comprising an input tunable matching network operatively connected to an input of the scalable periphery amplifier, the input tunable matching network being configured to adjust an input impedance of the input of the scalable periphery amplifier.

36. The amplifier according to claim 34, wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

37. The amplifier according to claim 35, wherein each unit cell of the one or more unit cells is a biased unit cell, a bias being applied to said biased unit cell.

38. The amplifier according to any one of claims 34, 35, 36 or 37, wherein the output tunable matching network is configured to be adjusted to switch an operation of the scalable periphery amplifier between two or more classes of amplifier operation.

39. The amplifier according to claim 38, wherein the output tunable matching network is configured to affect a harmonic termination of the amplifier according to a desired class of amplifier operation.

40. The amplifier according to claim 38, wherein the output tunable matching network is configured to affect a harmonic termination of the amplifier according to a desired operating characteristic of the amplifier.

41. The amplifier according to claim 40, wherein the desired operating characteristic of the amplifier comprises one or more of:

a) an adjacent channel leakage ratio in correspondence to an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

42. The amplifier according to any one of claims 34, 35, 36 or 37, wherein the amplifier control circuitry is configured to switch an operation of one or more of the unit cells between two or more classes of amplifier operation.

43. The amplifier according to any one of claims 34, 35, 36 or 37, wherein the amplifier control circuitry is configured to select a first class of amplifier operation in correspondence of a first group of unit cells and a second class of amplifier operation in correspondence of a second group of unit cells, wherein the first group of unit cells and the second group of unit cells comprise one or more unit cells from the one or more unit cells.

44. The amplifier according to any one of claims 34, 35, 36 or 37, wherein one or more of:

a) the amplifier control circuitry, and b) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

45. The amplifier according to claim 35 or claim 37, wherein one or more of:

a) the amplifier control circuitry, b) the input tunable matching network, and c) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

46. The amplifier according to claim 36 or claim 37, wherein one or more of:

a) the amplifier control circuitry, b) the output tunable matching network, and c) the bias applied to the one or more unit cells, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

47. The amplifier according to claim 37, wherein one or more of:

a) the amplifier control circuitry, b) the input tunable matching network, c) the bias applied to the one or more unit cells, and d) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

48. The amplifier according to claim 44, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

49. The amplifier according to claim 45, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage used to provide main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

50. The amplifier according to claim 46, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage used to provide main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

51. The amplifier according to claim 47, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

52. The amplifier according to claim 48, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

53. The amplifier according to claim 52, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

54. The amplifier according to claim 53, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

55. The amplifier according to claim 52, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

56. The amplifier according to claim 49, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

57. The amplifier according to claim 56, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

58. The amplifier according to claim 57, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

59. The amplifier according to claim 56, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

60. The amplifier according to claim 50, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

61. The amplifier according to claim 60, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

62. The amplifier according to claim 61, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

63. The amplifier according to claim 60, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

64. The amplifier according to claim 51, further comprising auxiliary circuitry, wherein the auxiliary circuitry is configured to maintain the desired operating characteristic of the amplifier over the range of varying parameters in one or more of:

a) a closed loop control configuration, and b) an open loop control configuration.

65. The amplifier according to claim 64, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

66. The amplifier according to claim 65, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

67. The amplifier according to claim 64, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

81. The amplifier according to any one of claims 2, 34 or 68, wherein the amplifier control circuitry is configured to maintain an operation of the amplifier in an AB Null class of operation by selectively activating and/or deactivating one or more unit cells in response to a varying output power.

82. The amplifier according to claim 81, wherein the varying output power is in correspondence of varying of one or more of:

a) a desired output power level of the amplifier, b) a battery voltage used to provide main power to the amplifier, c) a temperature of the amplifier, d) manufacturing tolerances of the amplifier, e) a band of operation of the amplifier, f) a frequency of operation of the amplifier, g) a peak-to-average ratio of the input signal to the amplifier, h) a modulation scheme of the input signal to the amplifier, i) a bandwidth of the input signal to the amplifier, and j) an input power level of the amplifier.

83. The amplifier according to any one of claims 2, 34 or 68, wherein one or more of the one or more unit cells comprise an input coupling capacitor operatively connected in a series configuration between the input signal and the input transistor, wherein the coupling capacitor is configured to remove a DC content from the input signal.

84. The amplifier according to any one of claims 2, 3, 4, 5, 34, 35, 36, 37, 68, 69 or 70, wherein each of the one or more unit cells comprises a switch connected in series with a gate of the input transistor of the stack, the switch being configured to open or close the input signal path to the input transistor, thus selectively activating or deactivating the one or more unit cells.

85. The amplifier according to claim 84, wherein a bias applied to a transistor of the stack other than the input transistor is configured to be adjusted in correspondence of activating or deactivating a corresponding unit cell.

86. The amplifier according to claim 84, wherein the switch is configured to selectively connect the gate of the input transistor to either the input signal or to a fixed voltage so as to selectively activate or deactivate the one or more unit cells.

87. The amplifier according to claim 2 or claim 34, wherein each of the one or more unit cells comprises a switch connected in series with a gate of any transistor other than an input transistor of the stack, the switch being configured to turn ON or turn OFF the transistor thus selectively activating or deactivating the one or more unit cells.

88. The amplifier according to claim 2 or claim 34, further comprising a current mirror operatively connected to the gates of the plurality of transistors of the stack, wherein the current mirror is adapted to provide biasing to the plurality of transistors.

89. The amplifier according to claim 88, wherein the current mirror is configured to selectively activate or deactivate a unit cell in correspondence of the plurality of transistors.

90. The amplifier according to any one of claims 2, 34 or 68, wherein the one or more unit cells have a same circuital arrangement.

91. The amplifier according to any one of claims 2, 34 or 68, wherein the output tunable matching network comprises:

one or more tunable reactive elements connected between the output of the scalable periphery amplifier and a load; and

a tunable matching control circuit configured to tune the one or more tunable reactive elements to adjust the output load impedance seen by the output of the scalable periphery amplifier.

92. The amplifier according to any one of claims 2, 34 or 68, wherein the output tunable matching network comprises:

a first set of one or more tunable reactive elements connected in series between the output of the scalable periphery amplifier and a load;

a second set of one or more tunable reactive elements connected in parallel between the output of the scalable periphery amplifier and the load; and

a tunable matching control circuitry configured to tune the first set of the one or more tunable reactive elements and the second set of the one or more tunable reactive elements, thus adjusting the output load impedance seen by the output of the scalable periphery amplifier.

93. The amplifier according to claim 91, wherein the one or more tunable reactive elements comprise one or more of:

a) one or more digital tuning capacitors, and b) one or more digital tuning inductors.

94. The amplifier according to claim 92, wherein the one or more tunable reactive elements comprise one or more of:

a) one or more digital tuning capacitors, and b) one or more digital tuning inductors.

95. The amplifier according to any one of claims 2, 34 or 68, wherein the output tunable matching network comprises a plurality of tunable matching networks operatively coupled in one or more of:

a) a π

-configuration, b) a t-configuration, and c) a cascade configuration, so as to achieve a desired bandwidth and/or quality factor.

96. The amplifier according to any one of claims 2, 34 or 68, wherein the output tunable matching network comprises one or more switches, the one or more switches being configured to adjust the output load impedance seen by the output of the scalable periphery amplifier.

97. The amplifier according to any one of claims 2, 34 or 68, wherein the scalable periphery amplifier is a monolithically integrated scalable periphery amplifier.

98. The amplifier according to claim 81, wherein the scalable periphery amplifier is a monolithically integrated scalable periphery amplifier.

99. The amplifier according to any one of claims 3, 35 or 69, wherein the scalable periphery amplifier and one or more of:

a) the input tunable matching network in entirety or in part, and b) the output tunable matching network in entirety or in part, are monolithically integrated.

100. The amplifier according to claim 92, wherein the scalable periphery amplifier and one or more of:

a) the output tunable matching network in entirety or in part, and b) the tunable matching control circuitry in entirety or in part, are monolithically integrated.

101. The amplifier according to any one of claims 4, 5, 36, 37 or 70, wherein a same bias is applied to each activated unit cell of the one or more unit cells.

102. The amplifier according to any one of claims 4, 5, 36, 37 or 70, wherein a direct current power P_DC of the amplifier is in correspondence of the bias applied to one or more activated unit cells of the one or more unit cells.

103. The amplifier according to claim 102, wherein a same value P_DC occurs upon activation of one of a plurality of groups of unit cells, each group of unit cells comprising one or more biased unit cells of the one or more unit cells.

104. The amplifier according to claim 103, wherein each unit cell of each group has a same bias and each group is biased differently.

105. The amplifier according to any one of claims 4, 5, 36, 37 or 70, wherein bias adjustment for each unit cell is adapted to switch an operation of the scalable periphery amplifier between two or more classes of amplifier operation.

106. The amplifier according to claim 2 or claim 34, wherein each transistor of the plurality of stacked transistors is a biased transistor.

107. The amplifier according to claim 106, wherein a bias applied to a transistor of the stack is configured to be adjusted in correspondence of activating or deactivating a corresponding unit cell.

108. The amplifier according to claim 106, wherein a bias applied to a transistor of the plurality of stacked transistors is configured to change such as to control equalization of a voltage across each transistor of the plurality of transistors.

109. The amplifier according to claim 108, wherein the change of the bias is performed using one of:

a) a switch configured to select one of several bias voltages to be applied to the transistor, and b) a circuital arrangement configured to vary the bias voltage applied to the transistor.

110. The amplifier according to claim 108, wherein a capacitor at a gate of the transistor of the plurality of stacked transistors is configured to allow a voltage swing at the gate of said transistor in correspondence of an output voltage swing at output of the stack.

111. The amplifier according to any one of claims 2, 34 or 68, wherein the one or more unit cells are made with a semiconductor process selected from the group consisting of:

a) gallium arsenide, b) complementary metal oxide semiconductor, c) silicon germanium, d) bipolar, e) gallium nitride, f) silicon on insulator (SOI) technology, and g) silicon on sapphire (SOS) technology.

112. The amplifier according to any one of claims 2, 34 or 68, wherein the amplifier control circuitry comprises complementary metal oxide semiconductor (CMOS) transistors fabricated using one or more of:

a) bipolar CMOS technology, b) silicon on insulator (SOI) technology, c) silicon on sapphire technology (SOS), and d) CMOS.

113. The amplifier according to claim 2 or claim 34, wherein the plurality of stacked transistors are operatively configured in any one of or any combination of a) a cascode configuration, b) a push-pull configuration, and c) a differential configuration.

114. The amplifier according to claim 2 or claim 34, wherein the plurality of stacked transistors are one of:

a) of a same type, and b) of different types.

115. The amplifier according to claim 2 or claim 34, wherein the plurality of stacked transistors are of N-type and P-type configured in a push-pull configuration.

116. The amplifier according to claim 115 comprising further circuital arrangement, wherein the further circuital arrangement is configured to switch on/off one or more transistors of the stack such as to affect an operation of the stack.

117. The amplifier according to claim 116, wherein the switching on/off of the one or more transistors of the stack affects a class of operation of the amplifier.

118. An amplifier system, comprising:

a plurality of amplifiers operatively connected together, each amplifier of the plurality of amplifiers comprising the amplifier according to claim 2 or claim 34; and

a plurality of switches operatively connected between successive amplifiers, wherein each switch is configured to direct an output of an amplifier to a subsequent amplifier or bypass the subsequent amplifier.

119. The amplifier system according to claim 118, wherein the plurality of amplifiers are operatively connected in a cascaded series.

120. The amplifier system according to claim 118, wherein the plurality of amplifiers comprise a driver amplifier and a final amplifier.

121. A cascaded series of amplifiers operatively coupled in series, wherein each amplifier of the cascaded series of amplifiers is the amplifier according to claim 2 or claim 34.

122. The cascaded series of amplifiers according to claim 121, comprising a driver stage amplifier and a final stage amplifier.

68. An amplifier, comprising:

a scalable periphery amplifier comprising one or more unit cells connected in parallel with each other and adapted to be selectively activated or deactivated, wherein at least one unit cell comprises one transistor configured to operate as an amplifier;

an output tunable matching network operatively connected to an output of the scalable periphery amplifier, wherein the tunable matching network is configured to adjust an output load impedance seen by the output of the scalable periphery amplifier; and

an amplifier control circuitry configured to selectively activate or deactivate the one or more unit cells, thus varying a total output power from the amplifier,

wherein the one transistor of the at least one unit cell is configured to receive an input signal of the scalable periphery amplifier.

69. The amplifier according to claim 68, further comprising an input tunable matching network operatively connected to an input of the scalable periphery amplifier, wherein an impedance of the input tunable matching network is configured to adjust relative to an input impedance of the input of the scalable periphery amplifier.

70. The amplifier according to claim 69, wherein each unit cell of the one or more unit cells is a biased unit cell, whereby the one transistor of the at least one unit cell is a biased transistor.

71. The amplifier according to claim 68, further comprising a current mirror operatively connected to a gate of the one transistor of the at least one unit cell, the current mirror being adapted to provide a biasing to the one transistor.

72. The amplifier according to claim 68, further comprising a switch connected in series to a gate of the one transistor of the at least one unit cell, the switch being configured to turn ON or turn OFF the transistor thus selectively activating or deactivating the at least one unit cell.

73. The amplifier according to claim 71, wherein the current mirror is configured to selectively activate or deactivate the at least one unit cell.

74. The amplifier according to any one of claims 68, 69 or 70, wherein the output tunable matching network is configured to be adjusted to switch an operation of the scalable periphery amplifier between two or more classes of amplifier operation.

75. The amplifier according to claim 74, wherein the output tunable matching network is configured to affect a harmonic termination of the amplifier according to a desired class of amplifier operation.

76. The amplifier according to any one of claims 68, 69 or 70, wherein one or more of:

a) the amplifier control circuitry, b) the input tunable matching network, c) the bias applied to the one or more unit cells, and d) the output tunable matching network, are configured to affect a desired operating characteristic of the amplifier, the desired operating characteristic of the amplifier comprising one or more of;

a) an adjacent channel leakage ratio in correspondence of an output signal power level, b) a power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

77. The amplifier according to claim 76, further configured to maintain the desired operating characteristic of the amplifier over a range of varying parameters, the varying parameters comprising one or more of:

a) a battery voltage providing main power to the amplifier, b) a temperature of the amplifier, c) manufacturing tolerances of the amplifier, d) a band of operation of the amplifier, e) a frequency of operation of the amplifier, f) a peak-to-average ratio of the input signal to the amplifier, g) a modulation scheme of the input signal to the amplifier, h) a bandwidth of the input signal to the amplifier, and i) an input power level of the amplifier.

78. The amplifier according to claim 77, wherein the open/closed loop control configurations comprise lookup tables and/or calibration tables stored in hardware and/or software.

79. The amplifier according to claim 78, wherein the auxiliary circuitry further comprises the hardware lookup tables and/or calibration tables.

80. The amplifier according to claim 77, wherein the scalable periphery amplifier and one or more of:

a) the amplifier control circuitry in entirety or in part, b) the auxiliary circuitry in entirety or in part, c) the tunable matching network in entirety or in part, and d) the output tunable matching network in entirety or in part, are monolithically integrated.

123. A method of biasing a scalable periphery amplifier, the method comprising:

providing a plurality of amplifiers of the scalable periphery amplifier, wherein each amplifier of the plurality of amplifiers of the scalable periphery amplifier comprises a plurality of transistors configured in a stacked arrangement;

operatively coupling the plurality of amplifiers in a parallel arrangement;

providing an input power range for an input signal to the plurality of amplifiers of the scalable periphery amplifier;

providing a desired power gain of the scalable periphery amplifier;

obtaining an expected output power range of the scalable periphery amplifier based on the desired power gain and the input power range, and

based on the obtaining, activating one or more amplifiers from the plurality of amplifiers.

124. The method according to claim 123, further comprising:

coupling an output tunable matching network to an output of the amplifiers;

coupling an input tunable matching network to an input of the amplifiers;

providing a desired output signal characteristic of the output of the amplifiers, and

adjusting one or more of;

a) the input tunable matching network, b) the output tunable matching network, c) the number of the one or more activated amplifiers, and d) a DC bias current of the one or more activated amplifiers, wherein the adjusting is based on the desired output signal characteristic.

125. The method according to claim 124, further comprising:

providing a set of varying parameters affecting an output signal characteristic of the output of the amplifiers;

providing circuitry configured to detect the set of varying parameters;

measuring a time varying value of the set of varying parameters;

providing a desired operating margin in correspondence of the desired output signal characteristic;

further adjusting one or more of a), b), c) or d) based upon the measuring;

operating within the desired operating margin as a consequence of the further adjusting.

126. The method according to claim 125, further comprising:

providing control circuitry adapted to perform the further adjustment based on the set of varying parameters;

feeding the measured time varying value of the set of varying parameters to the control circuitry;

operating within the desired operating margin in a close loop configuration as a consequence of the feeding.

129. The method according to any one of claims 124, 125, 126, or 127, wherein the desired output signal characteristic is one of:

a) adjacent channel leakage ratio (ACLR) in correspondence of the output signal power level, and b) power added efficiency (PAE) in correspondence of the output signal power level, c) an output power level, d) a drain current at an output of the amplifier, e) an out of band emission in correspondence of the output signal power level, f) an R_X band noise, in correspondence of the output signal power level, and g) an error vector magnitude in correspondence of the output signal power level.

130. The method according to claim 125 or claim 126, wherein the set of varying parameters comprises one or more of:

a) a battery voltage providing main power to the plurality of amplifiers, b) a temperature of the plurality of amplifiers, c) manufacturing tolerances of the plurality of amplifiers, d) a band of operation of the plurality of amplifiers, e) a frequency of operation of the plurality of amplifiers, f) a peak-to-average ratio of the input signal to the plurality of amplifiers, g) a modulation scheme of the input signal to the plurality of amplifiers, h) a bandwidth of the input signal to the plurality of amplifiers, and i) an output power level of the plurality of amplifiers.

131. The method according to claim 123, wherein the activating shifts an AB Null characteristic of the scalable periphery amplifier within the expected output power range.

132. The method according to claim 123 or claim 131, wherein activating is further based on data stored within a lookup table.

127. A method of amplifying an input signal, the method comprising:

providing a plurality of amplifiers, wherein each amplifier of the plurality of amplifiers comprises a plurality of transistors configured in a stacked arrangement;

operatively coupling the plurality of amplifiers in a parallel arrangement;

providing a plurality of switches configured to selectively activate or deactivate the plurality of amplifiers;

coupling a tunable matching network to an input port of the plurality of amplifiers;

inputting an input signal to the tunable matching network;

measuring the input signal power level;

activating one or more amplifiers from the plurality of amplifiers based on the input signal power level and on a desired output signal power level, and

adjusting an impedance of the tunable matching network in correspondence of an input signal power level shift in correspondence of further activating or deactivating of the one or more amplifiers from the plurality of amplifiers, wherein the further activating or deactivating of the one or more amplifiers is in correspondence of a desired output signal characteristic.

128. The method according to claim 127 further comprising:

coupling a tunable matching network to an output of the plurality of amplifiers;

tuning the tunable matching network as a consequence of the activating of the one or more amplifiers, and

providing a constant output load to an output of each of the one or more activated amplifiers as a consequence of the tuning.

133. A method of affecting a class of operation of an scalable periphery amplifier, the method comprising:

providing a plurality of amplifiers, wherein each amplifier of the plurality of amplifiers comprises a plurality of transistors configured in a stacked arrangement;

operatively coupling the plurality of amplifiers in a parallel arrangement;

providing a plurality of switches configured to selectively activate or deactivate the plurality of amplifiers;

coupling a tunable matching network to an output port of the plurality of amplifiers;

providing a desired class of operation of the scalable periphery amplifier

tuning the tunable matching network;

based on the tuning, adjusting a harmonic termination at the output of the plurality of amplifiers, and

based on the adjusting, affecting a class of operation of the scalable periphery amplifier, wherein the affecting changes the class of operation of the SP amplifier to the desired class of operation.

134. A system comprising:

an amplifying arrangement comprising one or more amplifying components connected with each other and adapted to be independently activated or deactivated, each amplifying component comprising one or more active devices configured to operate as amplifiers;

an output tunable matching network operatively connected to an output of the scalable periphery amplifier, the tunable matching network being configured to adjust an output load impedance seen by the output of the amplifying arrangement; and

control circuitry configured to independently activate or deactivate the one or amplifying components, thus varying a total output power from the amplifier,

wherein at least one amplifying component of the one or more amplifying components comprises a stack of active devices.