Current Balancing, Current Sensor, and Phase Balancing Apparatus and Method for a Voltage Regulator

• US 20140266832A1
• Filed: 06/28/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Alexander Lyakhov, Gerhard Schrom, Hodgson J. Keith, Narayanan Natarajan
• Inventors: HODGSON, J. Keith, LYAKHOV, Alexander, TANG, Chiu Keung, RAGHURAMAN, Narayanan, NATARAJAN, Narayanan, SCHROM, Gerhard
• Granted Patent: US 8,890,737 B2
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1566 with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array

Abstract

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Claims

1. An apparatus comprising:

a plurality of inductors coupled to a capacitor and a load;

a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and

a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

2. The apparatus of claim 1 further comprises a circuit to generate an average current using sensed current from each of the current sensors of the plurality of current sensors.

3. The apparatus of claim 2 further comprises:

a wave generator to generate a plurality of wave signals;

a plurality of comparators to generate a plurality of phase width modulated (PWM) signals; and

a plurality of resistors, each of which is coupled to a comparator of the plurality of comparators, and coupled to the wave generator.

4. The apparatus of claim 3, wherein each resistor of the plurality of resistors to generate an error current from a difference of the average current and a corresponding sensed current of the bridge.

5. The apparatus of claim 3, wherein each resistor of the plurality of resistors to generate a direct current (DC) voltage to adjust a DC level of a wave signal from the plurality of wave signals.

6. The apparatus of claim 4, wherein each comparator to adjust duty cycle of its generated PWM signal according to the DC voltage generated by the resistor coupled to the comparator.

7. The apparatus of claim 3, wherein the wave generator to generate the plurality of wave signals which are triangular waves.

8. The apparatus of claim 3 further comprises a circuit for cancelling input offset of each comparator of the plurality of comparators.

9. The apparatus of claim 2 further comprises an over-current protection circuit to receive the average current and to generate an over-current protection signal according to the average current.

10. The apparatus of claim 2 further comprises a power control unit (PCU) to receive the average current.

11. The apparatus of claim 1 wherein each current sensor comprises:

a first current sensor for sensing current through a high-side switch of the bridge; and

a second current sensor for sensing current through a low-side switch of the bridge.

12. The apparatus of claim 11, wherein the first and second current sensors include a common gate amplifier.

13. The apparatus of claim 11, wherein each of the first and second current sensors to generate a corresponding differential current output.

14. The apparatus of claim 13 further comprises a circuit to convert the corresponding differential current output to a corresponding single-ended current output.

15. The apparatus of claim 11, wherein the first current sensor is coupled to the second current sensor to generate a combined differential current output.

16. The apparatus of claim 15 further comprises a circuit to convert the combined differential current output to a single ended current output.

17. A system comprising:

a memory unit;

a processor coupled to the memory unit, the processor including;

a plurality of inductors coupled to a capacitor and a load;

a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and

a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge; and

a wireless interface for allowing the processor to communicate with another device.

18. The system of claim 17 further comprises a display unit.

19. The system of claim 17, wherein the processor further comprises:

circuit to generate an average current using sensed current from each of the current sensors of the plurality of current sensors;

a wave generator to generate a plurality of wave signals;

a plurality of comparators to generate a plurality of phase width modulated (PWM) signals; and

a plurality of resistors, each of which is coupled to a comparator of the plurality of comparators, and coupled to the wave generator.

20. The system of claim 19, wherein each resistor of the plurality of resistors to generate an error current from a difference of the average current and a corresponding sensed current of the bridge.

21. A current digital-to-analog converter (DAC) comprising:

a plurality of n-type devices, gate terminals of which are coupled to a first control signal, wherein source terminal of each of the n-type devices is coupled to ground; and

a plurality of switches, for coupling drain terminals of some or all of the n-type devices with one another, to generate a first current output.

22. The current DAC of claim 21 further comprises:

a plurality of p-type devices, gate terminals of which are coupled to a second control signal, wherein source terminal of each of the p-type devices is coupled to a power supply; and

a plurality of switches, for coupling drain terminals of some or all of the p-type devices with one another, to generate a second current output.

23. The current DAC of claim 22 further comprises:

an output node for coupling the first and second current outputs.

24. The current DAC of claim 23, wherein the plurality of p-type and n-type devices are controlled by digital signals to cause any of the plurality of p-type and n-type devices to turn on or off.

25. The current DAC of claim 24, wherein the digital signals are a binary code, and wherein the output node to generate a monotonic change in current according to the binary code.