CURRENT SATURATION DETECTION AND CLAMPING CIRCUIT AND METHOD

• US 20140268435A1
• Filed: 03/14/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Beck, Riley D., Layton, Kent D.
• Granted Patent: US 9,124,094 B2
• Time in Patent Office: Days
• US Class Current: 361/42
• CPC Class Codes: H02H 3/283 and taking into account saturation of current transformers
• CPC Class Codes: H02H 3/33 using summation current transformers H02H3/347 takes precedence

Abstract

A method and circuit for detecting and clamping current in a ground fault circuit interrupter circuit. In accordance with an embodiment the circuit includes an amplifier connected to a switch, where in the amplifier has an input connected to a first conduction terminal of the switch through a resistor and another input connected to a second conduction terminal of the switch. An output of the amplifier is connected to a control terminal of the switch. The circuit may include a ground fault circuit interrupter engine having an input connected to the first conduction terminal of the switch and another second input connected to the second conduction terminal of the switch.

Claims

1. A current saturation detection and clamping circuit, comprising:

a switch having a control terminal and first and second conduction terminals;

a first amplifier having first and second inputs and first and second outputs, the first input coupled to the second conduction terminal of the switch and the first output coupled to the control terminal of the switch;

a first impedance coupled between the second input of the first amplifier and the first conduction terminal of the switch; and

a ground fault circuit interrupter engine having first and second inputs, the first input coupled to the first conduction terminal of the switch and the second input coupled to the second conduction terminal of the switch.

2. The current saturation detection and clamping circuit of claim 1, further including a second amplifier having first and second inputs and first and second outputs, the first input coupled to the second conduction terminal of the switch and the first output coupled to the control terminal of the switch.

3. The current saturation detection and clamping circuit of claim 2, further including a second impedance coupled between the second input of the second amplifier and the first current conductor of the switch.

4. The current saturation detection and clamping circuit of claim 1, further including a first current source coupled to the second input of the first operational amplifier.

5. The current saturation detection and clamping circuit of claim 4, further including a second current source coupled to the second input of the second operational amplifier.

6. The current saturation detection and clamping circuit of claim 1, wherein the ground fault circuit interrupter further comprises a third input, and further including a saturation indicator circuit having first and second inputs and an output, the first input coupled to the second output of the first amplifier and the output coupled to the third input of the ground fault circuit interrupter.

7. The current saturation detection and clamping circuit of claim 6, wherein the second output of the second amplifier is coupled to the second input of the saturation indicator circuit.

8. The current saturation detection and clamping circuit of claim 6, wherein the saturation indicator circuit comprises an OR gate.

9. A circuit, comprising:

a transistor having a control electrode and first and second current carrying electrodes;

a ground fault circuit interrupter engine having a plurality of inputs, a first input of the plurality of inputs coupled to the first current carrying electrode of the transistor and a second input of the plurality of inputs coupled to the second current carrying electrode of the transistor; and

a drive circuit having a plurality of inputs and an output, the output coupled to the control electrode of the transistor.

10. The circuit of claim 9, wherein the drive circuit comprises:

a first gain stage having first and second inputs and first and second outputs, the first input coupled to the second current carrying electrode of the transistor and serving as a first input of the plurality of inputs; and

a second gain stage having first and second inputs and first and second outputs, the first input coupled to the second current carrying electrode of the transistor and serving as a second input of the plurality of inputs and the output coupled to the control electrode of the transistor, the outputs of the first and second gain stages coupled together to form the output of the drive circuit.

11. The circuit of claim 10, further including a bias network having first and second terminals and a common node, the first terminal coupled to the second input of the first gain stage, the second terminal coupled to the second input of the second gain stage, and the first current carrying electrode of the transistor coupled to the common node.

12. The circuit of claim 11, wherein the bias network comprises:

a first resistor having first and second terminals, the first terminal coupled to the second input of the first gain stage and serving as the first terminal of the bias network; and

a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor to form the common node, the second terminal of the second resistor coupled to the second input of the second gain stage and serving as the second terminal of the bias network.

13. The circuit of claim 12, wherein the bias network further comprises:

a first current source coupled to the second input of the first gain stage; and

a second current source coupled to the second input of the second gain stage.

14. The circuit of claim 12, further including a saturation indicator circuit having first and second inputs and an output, the first input coupled to the second output of the first gain stage and the second input coupled to the second output of the second gain stage.

15. The circuit of claim 13, wherein the saturation indicator circuit comprises an OR gate.

16. The circuit of claim 13, further including a current transformer having first and second terminals, the first terminal coupled to the first current carrying electrode of the transistor and the second terminal coupled to the second current carrying electrode of the transistor.

17. A method for detecting a fault condition, comprising:

detecting a differential current level of a current flowing in a power mains;

activating a current shunt in response to the differential current level generating a voltage at a node that one of exceeds a first reference voltage or is less than a second reference voltage;

clamping the voltage at the node at the first reference voltage in response to the voltage at the node exceeding the first reference voltage or clamping the voltage at the node at the second reference voltage in response to the voltage at the node being less than the second reference voltage;

generating a saturation signal in response to clamping the voltage at the node; and

generating a fault detection signal in response to the saturation signal being asserted for a predetermined time.

18. The method of claim 17, wherein activating the current shunt includes turning on a transistor in response to a difference in voltages at first and second inputs of a first amplifier being greater than a predetermined value.

19. The method of claim 17, further including generating the saturation signal in response to at least one output signal from an amplifier being at a logic high voltage level.

20. The method of claim 17, wherein activating the current shunt includes shunting a current to a current transformer.