VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF DRIVING THE SAME

• US 20140268996A1
• Filed: 07/25/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Nam Kyun
• Granted Patent: US 9,666,642 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/061 Patterning of the switching material
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer.

Claims

1. A variable resistance memory device, comprising:

a base layer;

a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer;

a current transfer layer formed to surround the pillar-shaped gate electrode;

a variable resistance layer formed in an outer portion of the current transfer layer; and

a blocking layer configured o;

block a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and

divert the current flowing through the current transfer layer to the variable resistance layer.

2. The variable resistance memory device of claim 1, wherein the pillar-shaped gate electrode is formed of a first conductivity-type semiconductor layer and the current transfer layer is formed of a second conductivity-type semiconductor layer.

3. The variable resistance memory device of claim 2, wherein the blocking layer is a depletion layer generated in the current transfer layer, when a reverse bias voltage is applied to the pillar-shaped gate electrode.

4. The variable resistance memory device of claim 1, wherein the pillar-shaped gate electrode is formed of a refractory metal layer and the current transfer layer is formed of a semiconductor layer having a conductivity-type.

5. The variable resistance memory device of claim 4, further comprising:

a silicide layer interposed between the pillar-shaped gate electrode and the current transfer layer.

6. The variable resistance memory device of claim wherein the pillar-shaped gate electrode is formed of a conductive material and the current transfer layer is formed of a predetermined conductivity-type semiconductor layer.

7. The variable resistance memory device of claim 6, further comprising:

a junction layer interposed between the pillar-shaped gate electrode and the current transfer layer; and

a gate insulating layer interposed between the pillar-shaped gate electrode and the junction layer.

8. The variable resistance memory device of claim 7, wherein the junction layer is formed to have an opposite conductivity type to a conductivity type of the current transfer layer, and

the junction layer forms a channel that serve as the blocking layer based on the voltage applied to the pillar-shaped gate electrode.

9. The variable resistance memory device of claim wherein the base layer includes an insulating material.

10. A variable resistance memory device, comprising:

a base layer;

a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer;

a plurality of bit lines alternately stacked with a plurality of insulating layers around the pillar-shaped gate electrode;

a plurality of variable resistance layers formed in outer portions of the plurality of bit lines; and

a plurality of blocking layers configured to;

block paths of currents flowing through the plurality of bit lines based on a voltage applied voltage to the pillar-shaped gate electrode, and

divert the currents flowing through the plurality of bit lines to the plurality of variable resistance layers.

11. The variable resistance memory device of claim 10, wherein the pillar-shaped gate electrode is formed of a first conductivity-type semiconductor layer and the plurality of bit lines are formed of a second conductivity-type semiconductor layer.

12. The variable resistance memory device of claim 11, wherein the plurality of blocking layers are depletion layers formed in the plurality of bit lines, when a reverse bias voltage is applied to the pillar-shaped gate electrode.

13. The variable resistance memory device of claim 10, wherein the pillar-shaped gate electrode is formed of a refractory metal layer and the plurality of bit lines are formed of a semiconductor layer having a conductivity-type.

14. The variable resistance memory device of claim 13, further comprising:

a plurality of silicide layers interposed between the pillar-shaped gate electrode and the plurality of bit lines.

15. The variable resistance memory device of claim 10, wherein the pillar-shaped gate electrode is formed of a conductive material and the plurality of bit lines are formed of a predetermined conductivity-type semiconductor layer.

16. The variable resistance memory device of claim 15, further comprising:

a plurality of junction layers interposed between the pillar-shaped gate electrode and the plurality of bit lines; and

a gate insulating layer interposed between the pillar-shaped gate electrode and each of the junction layers.

17. The variable resistance memory device of claim 16, wherein the plurality of junction layers are formed to have an opposite conductivity type to a conductivity type of the plurality of bit lines, and

the plurality of junction layers form channels that serve as the blocking layers based on the voltage applied to the pillar-shaped gate electrode.

18. The variable resistance memory device of claim 10, wherein the base layer include an insulating material.

19. A method of driving a variable resistance memory device, the method comprising:

forming a pillar-shaped gate electrode on a base substrate;

forming a bit line to surround the pillar-shaped gate electrode;

forming a variable resistance layer in an outer portion of the bit line; and

changing a path of a current flowing through the bit line to flow through the variable resistance layer based on a voltage applied to the pillar-shaped gate electrode.

20. The method of claim 19, further comprising:

forming, based on the voltage applied to the pillar-shaped gate electrode, a current block layer around the pillar-shaped gate electrode;

blocking, using the current block layer, the current flowing through the bit line, and

diverting, using the blocking layer, the current flowing through the bit line into the variable resistance layer.