INTEGRATED CAPACITOR BASED POWER DISTRIBUTION

• US 20140269034A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Manipatruni, Sasikanth, Nikonov, Dmitri E., Young, Ian A.
• Granted Patent: US 9,305,629 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.

Claims

1. An apparatus comprising:

a supply voltage plane that includes an array of supply voltage lines;

a ground plane that includes an array of ground lines;

an array of capacitors formed from the arrays of supply voltage lines and ground lines;

a first capacitor, formed at a first intersection between a first supply voltage line, included in the array of supply voltage lines, and a first ground line, included in the array of ground lines;

wherein the capacitor comprises a first plate that includes a portion of the first supply voltage line, a second plate that includes a portion of a first ground line, and a first dielectric formed between the first and second plates;

a device, to electrically couple to the capacitor, comprising at least one of a tunnel field-effect transistor, spin transfer torque (STT) memory, and a spin logic device; and

a switching element coupled to the capacitor and included within a switching mode power supply;

wherein (a) the array of capacitors, which includes the first capacitor, the device, and the switching element are all formed on a single monolithic substrate; and

(b) the switching element discharges the capacitor to drive current between the first and second plates and then to the device.

2. The apparatus of claim 1 comprising:

a second capacitor, formed at a second intersection between a second supply voltage line, included in the array of supply voltage lines, and a second ground line, included in the array of ground lines;

wherein the second capacitor comprises an additional first plate that includes a portion of the second supply voltage line, an additional second plate that includes a portion of a second ground line, and a second dielectric formed between the additional first and second plates;

wherein the power supply charges the first and second capacitors in series with one another during a charging mode and discharges the first and second capacitors in parallel with one another during a discharge mode.

3. The apparatus of claim 1, wherein the array of capacitors are metal-insulator-metal (MiM) capacitors.

4. The apparatus of claim 1, wherein:

the switching element includes first, second, and third switching devices;

the power supply charges the first capacitor during a first clock phase and discharges the first capacitor during a second clock phase that is opposite the first clock phase; and

the first switching device is active during the first clock phase and the second and third switching devices are active during the second clock phase.

5. The apparatus of claim 1, wherein the power supply discharges the first capacitor orthogonally to the supply voltage plane to drive current between the first and second plates and then to the device.

6. The apparatus of claim 5, wherein the power supply is a step down converter that steps supply voltage down from more than 1 V to less than 15 mV and supplies current greater than 90 A with a current density greater than 380 A/cm².

7. The apparatus of claim 1 comprising an interconnect coupling the device to one of the first and second plates, wherein an axis orthogonal to the second plate intersects the first and second plates and the device.

8. The apparatus of claim 1 wherein the first dielectric includes at least one of Hafnium Oxide, Ruthenium Oxide, Molybdenum Oxide, and LiMn₂O₄ activated carbon.

9. The apparatus of claim 1 wherein the entire power supply is included on the substrate and is to couple to a battery located off the substrate.

10. An apparatus comprising:

a supply voltage plane that includes a plurality of supply voltage lines;

a ground plane that includes a plurality of ground lines;

a plurality of capacitors each having a first terminal formed from one of the supply voltage lines and a second terminal formed from one of the ground lines; and

a non-CMOS based device to electrically couple to a capacitor included in the plurality of capacitors;

wherein the capacitors and the device are both formed on a single monolithic substrate.

11. The apparatus of claim 10 comprising a switching element coupled to the capacitor.

12. The apparatus of claim 11, wherein the switching element discharges the capacitor to drive current between the first and second terminals and through the device.

13. The apparatus of claim 11 wherein the switching element discharges the capacitor to drive current from a power supply to the capacitor and between the first and second terminals.

14. The apparatus of claim 11 wherein the device is at least one of a tunnel field-effect transistor, spin transfer torque (STT) memory, and a spin logic device.

15. An apparatus comprising:

a capacitor including a first plate that includes a portion of a voltage line, a second plate that includes a portion of a ground line, and a dielectric formed between the first and second plates;

a spintronic device coupled to the capacitor; and

a switch element coupled to the capacitor and included in a switch mode power supply;

wherein the capacitor, the device, and the switch element are all formed on a single monolithic substrate; and

(b) the switch element discharges the capacitor to drive current between the first and second plates and then to the device.

16. The apparatus of claim 15 comprising:

an additional capacitor including an additional first plate that includes a portion of an additional voltage line and an additional second plate that includes a portion of an additional ground line, and an additional dielectric formed between the first and second plates;

wherein the power supply charges the first and second capacitors in series with one another and discharges the first and second capacitors in parallel with one another.

17. The apparatus of claim 15, wherein:

the switch element includes first and second transistors;

the power supply charges the capacitor during a first clock phase and discharges the capacitor during a second clock phase; and

the switch device is active during the first clock phase and the second switch device is active during the second clock phase.

18. The apparatus of claim 15, wherein the power supply discharges the capacitor orthogonally to a supply voltage plane that includes the voltage line.

19. The apparatus of claim 15, wherein the power supply is a step down converter that steps supply voltage down from more than 1 V to less than 15 mV and supplies current greater than 90 A with a current density greater than 380 A/cm2.

20. The apparatus of claim 15, wherein an axis orthogonal to the second plate intersects the first and second plates and the device.

21. The apparatus of claim 15 wherein the dielectric includes at least one of Hafnium Oxide, Ruthenium Oxide, Molybdenum Oxide, and LiMn2O4 activated carbon.

22. The apparatus of claim 15 wherein the entire power supply is included on the substrate and is to couple to a battery located off the substrate.