CROSS POINT ARRAY MRAM HAVING SPIN HALL MTJ DEVICES
First Claim
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1. A bit cell for a non-volatile memory, the bit cell, comprising:
- a magnetic tunnel junction (MTJ) stack disposed above a substrate and comprising a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer; and
a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack.
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Abstract
Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack.
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Citations
21 Claims
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1. A bit cell for a non-volatile memory, the bit cell, comprising:
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a magnetic tunnel junction (MTJ) stack disposed above a substrate and comprising a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer; and a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:
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a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack; a plurality of select lines, each select line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells; a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells; and a plurality of word lines, each word line coupled to one or more of the plurality of bit cells at the second electrode of each of the one or more of the plurality of bit cells. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method of writing a logic 1 to a bit cell in a cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:
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identifying a target bit cell in a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack; increasing, to a write voltage a bit line voltage of a bit line coupled to the target bit cell, the bit line selected from a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells; and reducing to ground a select line voltage of a select line coupled to the bit cell, the select line from a plurality of select lines having a high impedence condition, each select line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells. - View Dependent Claims (15, 16, 17)
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18. A method of writing a logic 0 to a bit cell in a cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:
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identifying a target bit cell in a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack; decreasing, to a negative write voltage a bit line voltage of a bit line coupled to the target bit cell, the bit line selected from a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells; and reducing to ground a select line voltage of a select line coupled to the bit cell, the select line from a plurality of select lines having a high impedence condition, each select line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells. - View Dependent Claims (19, 20, 21)
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Specification