CROSS POINT ARRAY MRAM HAVING SPIN HALL MTJ DEVICES

• US 20140269035A1
• Filed: 03/14/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Manipatruni, Sasikanth, Nikonov, Dmitri E., Young, Ian A.
• Granted Patent: US 9,460,768 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack.

Claims

1. A bit cell for a non-volatile memory, the bit cell, comprising:

a magnetic tunnel junction (MTJ) stack disposed above a substrate and comprising a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer; and

a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack.

2. The bit cell of claim 1, wherein the spin hall metal electrode comprises a metal selected from the group consisting of β

-Tantalum (β

-Ta), β

-Tungsten (β

-W) and platinum (Pt), the metal disposed on the free magnetic layer.

3. The bit cell of claim 2, wherein the spin hall electrode comprises a second, different, metal on either side of the free magnetic layer.

4. The bit cell of claim 1, wherein the spin hall metal electrode is disposed on the free magnetic layer, the free magnetic layer is disposed on the dielectric layer, the dielectric layer is disposed on the fixed magnetic layer, and the bit cell further comprises:

a bottom electrode;

an anti-ferromagnetic (AFM) layer disposed on the bottom electrode; and

a synthetic anti-ferromagnet (SAF) stack disposed on the AFM layer, wherein the MTJ stack is disposed on the SAF stack.

5. The bit cell of claim 4, wherein the free magnetic layer comprises CoFeB, the dielectric layer comprises magnesium oxide (MgO), the fixed magnetic layer comprises CoFeB, the SAF stack comprises a layer of ruthenium (Ru) disposed on a layer of CoFe, the AFM layer comprises IrMn, and the bottom electrode comprises a Ru/Ta/Ru stack.

6. The bit cell of claim 1, wherein the spin hall metal electrode comprises a first end and a second end, the MTJ stack is disposed between the first and second ends, and wherein the bit cell further comprises:

a bottom electrode, the MTJ stack disposed above, and coupled to, the bottom electrode;

a word line coupled to the bottom electrode;

a select line coupled to the first end of the spin hall metal electrode; and

a bit line coupled to the second end of the spin hall metal electrode.

7. A cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:

a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack;

a plurality of select lines, each select line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells;

a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells; and

a plurality of word lines, each word line coupled to one or more of the plurality of bit cells at the second electrode of each of the one or more of the plurality of bit cells.

8. The cross-point array GSHE-MRAM of claim 7, wherein the spin hall metal electrode of each bit cell comprises a metal selected from the group consisting of β

-Tantalum (β

-Ta), β

-Tungsten (β

-W) and platinum (Pt), the metal disposed on a free magnetic layer of the MTJ stack of the bit cell.

9. The cross-point array GSHE-MRAM of claim 8, wherein the spin hall electrode comprises a second, different, metal on either side of the free magnetic layer.

10. The cross-point array GSHE-MRAM of claim 7, wherein the spin hall metal electrode of each bit cell is disposed above a free magnetic layer of the MTJ stack of the bit cell, the free magnetic layer is disposed on a dielectric layer of the MTJ stack of the bit cell, the dielectric layer is disposed on a fixed magnetic layer of the MTJ stack of the bit cell, and each bit cell further comprises:

a bottom electrode;

an anti-ferromagnetic (AFM) layer disposed on the bottom electrode; and

a synthetic anti-ferromagnet (SAF) stack disposed on the AFM layer, wherein the MTJ stack is disposed on the SAF stack.

11. The cross-point array GSHE-MRAM of claim 10, wherein the free magnetic layer comprises CoFeB, the dielectric layer comprises magnesium oxide (MgO), the fixed magnetic layer comprises CoFeB, the SAF stack comprises a layer of ruthenium (Ru) disposed on a layer of CoFe, the AFM layer comprises IrMn, and the bottom electrode comprises a Ru/Ta/Ru stack.

12. The cross-point array GSHE-MRAM of claim 7, wherein the spin hall metal electrode of each bit cell is disposed below a free magnetic layer of the MTJ stack of the bit cell, the free magnetic layer is disposed below a dielectric layer of the MTJ stack of the bit cell, the dielectric layer is disposed below a fixed magnetic layer of the MTJ stack of the bit cell, and each bit cell further comprises:

a top electrode;

an anti-ferromagnetic (AFM) layer disposed below the bottom electrode; and

a synthetic anti-ferromagnet (SAF) stack disposed below the AFM layer, wherein the MTJ stack is disposed below the SAF stack.

13. The cross-point array GSHE-MRAM of claim 12, wherein the free magnetic layer comprises CoFeB, the dielectric layer comprises magnesium oxide (MgO), the fixed magnetic layer comprises CoFeB, the SAF stack comprises a layer of ruthenium (Ru) disposed on a layer of CoFe, the AFM layer comprises IrMn, and the top electrode comprises a Ru/Ta/Ru stack.

14. A method of writing a logic 1 to a bit cell in a cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:

identifying a target bit cell in a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack;

increasing, to a write voltage a bit line voltage of a bit line coupled to the target bit cell, the bit line selected from a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells; and

reducing to ground a select line voltage of a select line coupled to the bit cell, the select line from a plurality of select lines having a high impedence condition, each select line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells.

15. The method of claim 14, further comprising:

maintaining a plurality of word lines at high impedence, each word line coupled to one or more of the plurality of bit cells at the second electrode of each of the one or more of the plurality of bit cells.

16. The method of claim 14, wherein the spin hall metal electrode of each bit cell is disposed, with respect to an underlying substrate, above the MTJ stack.

17. The method of claim 14, wherein the spin hall metal electrode of each bit cell is disposed, with respect to an underlying substrate, above the MTJ stack.

18. A method of writing a logic 0 to a bit cell in a cross-point array giant spin hall effect magnetoresistive random access memory (GSHE-MRAM), comprising:

identifying a target bit cell in a plurality of bit cells, each bit cell comprising a spin hall metal electrode coupled with a magnetic tunnel junction (MTJ) stack, and a second electrode coupled with the MTJ stack;

decreasing, to a negative write voltage a bit line voltage of a bit line coupled to the target bit cell, the bit line selected from a plurality of bit lines, each bit line coupled to one or more of the plurality of bit cells at a first end of each spin hall metal electrode of the one or more of the plurality of bit cells; and

reducing to ground a select line voltage of a select line coupled to the bit cell, the select line from a plurality of select lines having a high impedence condition, each select line coupled to one or more of the plurality of bit cells at a second, different, end of each spin hall metal electrode of the one or more of the plurality of bit cells.

19. The method of claim 18, further comprising:

maintaining a plurality of word lines at high impedence, each word line coupled to one or more of the plurality of bit cells at the second electrode of each of the one or more of the plurality of bit cells.

20. The method of claim 18, wherein the spin hall metal electrode of each bit cell is disposed, with respect to an underlying substrate, above the MTJ stack.

21. The method of claim 18, wherein the spin hall metal electrode of each bit cell is disposed, with respect to an underlying substrate, above the MTJ stack.