ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD
First Claim
1. A sensing amplifier for a memory device, the memory device comprising first and second bit lines and at least one memory cell coupled to the first and second bit lines, the sensing amplifier comprising:
- a first node configured to be coupled to the first bit line;
a second node configured to be coupled to the second bit line;
an input device coupled to the first and second nodes, the input device configured togenerate a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, andgenerate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell; and
an output device coupled to the first node, the output device configured to output the first or second datum read out from the memory cell;
wherein the first current is greater than the second current.
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Abstract
A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
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Citations
20 Claims
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1. A sensing amplifier for a memory device, the memory device comprising first and second bit lines and at least one memory cell coupled to the first and second bit lines, the sensing amplifier comprising:
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a first node configured to be coupled to the first bit line; a second node configured to be coupled to the second bit line; an input device coupled to the first and second nodes, the input device configured to generate a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell; and an output device coupled to the first node, the output device configured to output the first or second datum read out from the memory cell; wherein the first current is greater than the second current. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device, comprising:
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at least one pair of bit lines including a first bit line and a second bit line; at least one memory cell coupled to the first and second bit lines; first through fourth transistors; and an output device; wherein the first and third transistors are coupled in series between a power supply voltage node and a reference node, the second and fourth transistors are coupled in series between the power supply voltage node and the reference node, the first transistor is coupled to the third transistor at a first node, the first node configured to be coupled to the first bit line, the first node is coupled to gates of the second and fourth transistors, and to the output device, the second transistor is coupled to the fourth transistor at a second node, the second node configured to be coupled to the second bit line, the second node is coupled to gates of the first and third transistors, and a ratio of a first drain current of the first transistor to a second drain current of the second transistor matches a ratio of a total capacitance loading of the first node to a total capacitance loading of the second node. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of designing a memory device, the method performed by at least one processor and comprising:
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determining a total capacitance loading of a first node of an asymmetric sensing amplifier; determining a total capacitance loading of a second node of the asymmetric sensing amplifier, the asymmetric sensing amplifier having complementary logic states at the first node and second node; and configuring at least one of a first circuit or a second circuit of the asymmetric sensing amplifier based on a ratio of the determined total capacitance loading of the first node to the determined total capacitance loading of the second node, the first circuit associated with the first node, the second circuit associated with the second node. - View Dependent Claims (19, 20)
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Specification