CIRCUIT FOR MEMORY WRITE DATA OPERATION

• US 20140269114A1
• Filed: 03/14/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Jung-Ping, LEE, Cheng Hung, HUANG, Chia-En, WU, Fu-An, CHIU, Chih-Chieh
• Granted Patent: US 9,117,510 B2
• Time in Patent Office: Days
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage.

Claims

1. An electrical circuit for improving a write data operation to a memory device electrically coupled to a supply voltage, said supply voltage having a specified nominal supply voltage level, comprising:

voltage adjustment circuitry, said voltage adjustment circuitry having at least one voltage level control signal output to selectably control said supply voltage to output one of a plurality of different voltages, at least one of the plurality of different voltages having a voltage level lower than said specified nominal supply voltage level;

timing adjustment circuitry, said timing adjustment circuitry having at least one voltage transition timing control signal output to selectably control said supply voltage to output one of a plurality of different selectable logical state transition timings; and

supply voltage circuitry, said supply voltage circuitry electrically coupled to said voltage adjustment circuitry having at least one voltage level control signal output, the at least one voltage level control signal output causing said supply voltage circuitry output one of a plurality of different voltages, at least one of said plurality of different voltages being selected and electrically coupled to said memory device to selectably decrease a voltage level provided to said memory device during said write data operation, and said supply voltage circuitry electrically coupled to said timing adjustment circuitry having at least one voltage transition timing control signal output, the at least one voltage transition timing control signal output causing said supply voltage circuitry to output one of said plurality of different selectable logical state transition timings to alter a length of time before said at least one of said plurality of different voltages transitions back to said specified nominal supply voltage level.

2. The electrical circuit of claim 1, wherein said at least one of said plurality of different voltages further comprises at least two different voltages having a lower voltage level than said specified nominal supply voltage level.

3. The electrical circuit of claim 1, further comprising:

voltage keeper circuitry, said voltage keeper circuitry having a first MOS transistor connected in series with a second MOS transistor between said nominal supply voltage and said reduced supply voltage, said first MOS transistor having a gate input electrically coupled to said reduced supply voltage, said second MOS transistor having a gate input electrically coupled to said reduced supply voltage.

4. The electrical circuit of claim 1, wherein said memory device is a SRAM.

5. The electrical circuit of claim 1, wherein said timing adjustment circuitry having a plurality of different selectable logical state transition timings further comprises at least three different selectable logical state transition timings.

6. The electrical circuit of claim 1, wherein said electrical circuit is a pulsed dynamic LCV circuit.

7. The electrical circuit of claim 1, wherein said voltage adjustment circuitry is a tracking and LCV level adjust (1) functional block portion of said pulsed dynamic LCV circuit.

8. The electrical circuit of claim 1, wherein said timing adjustment circuitry is an LCV charging back timing adjust (2) functional block portion of said pulsed dynamic LCV circuit.

9. The electrical circuit of claim 1, wherein said at least one of said plurality of different selectable output voltages having a lower voltage level than said specified nominal supply voltage level further comprises at least one different selectable output voltage having a lower voltage level than said specified nominal supply voltage level, and said timing adjustment circuitry having a plurality of different selectable logical state transition timings further comprises at least four different selectable logical state transition timings.

10. A method of improving a write data operation of an SRAM having a specified nominal supply voltage level, comprising:

selectably adjusting a reduction of voltage associated with said write data operation, said step of selectably adjusting a reduction of voltage comprising selecting between a nominal supply voltage and at least one reduced supply voltage;

selectably adjusting timing of a voltage transition associated with said write data operation from said at least one reduced supply voltage to said nominal supply voltage, said step of selectably adjusting timing of a voltage transition comprising selecting between a plurality of different delays for said voltage transition; and

performing said write data operation by first performing said step of selectably adjusting a reduction of voltage and then performing said step of selectably adjusting timing of a voltage transition.

11. The method of claim 10, wherein said at least one reduced supply voltage further comprises at least two different reduced supply voltages each having a lower voltage level than said nominal supply voltage level.

12. The method of claim 10, wherein said at least one reduced supply voltage further comprises at least three different reduced supply voltages each having a lower voltage level than said nominal supply voltage level.

13. The method of claim 10, wherein said at least one reduced supply voltage further comprises at least four different reduced supply voltages each having a lower voltage level than said nominal supply voltage level.

14. The method of claim 10, wherein said plurality of different delays for said voltage transition further comprises at least three different selectable delays for said voltage transition.

15. The method of claim 10, wherein said plurality of different delays for said voltage transition further comprises at least four different selectable delays for said voltage transition.

16. The method of claim 10, wherein said step of selectably adjusting a reduction of voltage associated with said write data operation is performed by a tracking and LCV level adjust (1) functional block portion of said pulsed dynamic LCV circuit.

17. The method of claim 10, wherein said step of selectably adjusting timing of a voltage transition associated with said write data operation from said at least one reduced supply voltage to said nominal supply voltage is performed by an LCV charging back timing adjust (2) functional block portion of said pulsed dynamic LCV circuit.

18. The method of claim 10, wherein said step of selectably adjusting a reduction of voltage associated with said write data operation is performed by a tracking and LCV level adjust (1) functional block portion of said pulsed dynamic LCV circuit and wherein said step of selectably adjusting timing of a voltage transition associated with said write data operation from said at least one reduced supply voltage to said nominal supply voltage is performed by an LCV charging back timing adjust (2) functional block portion of said pulsed dynamic LCV circuit.

19. An electrical circuit for improving a write data operation to an SRAM having a specified nominal supply voltage level, comprising:

voltage adjustment circuitry, said voltage adjustment circuitry having a plurality of differ selectable output voltages, at least one of said plurality of different selectable output voltages having a lower voltage level than said specified nominal supply voltage level;

voltage keeper circuitry, said voltage keeper circuitry having a first MOS transistor connected in series with a second MOS transistor between said nominal supply voltage and said reduced supply voltage, said first MOS transistor having a gate input electrically coupled to said reduced supply voltage, said second MOS transistor having a gate input electrically coupled to said reduced supply voltage.

timing adjustment circuitry, said timing adjustment circuitry having a plurality of different selectable logical state transition timings; and

adjustable power supply circuitry, said adjustable power supply circuitry electrically coupled to said voltage adjustment circuitry and said plurality of different selectable voltages, one of said at least one of said plurality of different selectable output voltages having a lower voltage level than said specified nominal supply voltage level being selected and electrically coupled to said SRAM to selectably decrease a voltage level provided to said SRAM during said write data operation, and said adjustable power supply circuitry electrically coupled to said timing adjustment circuitry and said plurality of different selectable logical state transition timings, one of said plurality of different selectable logical state transition timings being selected to alter a length of time before said at least one of said plurality of different selectable output voltages having a lower voltage level than said specified nominal supply voltage level transitions back to said specified nominal supply voltage level.

20. The pulsed dynamic LCV circuit of claim 19, wherein said first MOS transistor is a PMOS-type transistor and said second MOS transistor is a PMOS-type transistor.