RECEIVER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST METHOD

• US 20140269872A1
• Filed: 02/10/2014
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: ONODERA, Mitsuru
• Granted Patent: US 9,255,966 B2
• Time in Patent Office: Days
• US Class Current: 375/226
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: H04L 1/205 jitter monitoring

Abstract

A receiver circuit includes a CDR circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude). The test pattern generator unit generates a test pattern to which the jitter is added, and supplies the test pattern to the CDR circuit. The comparator unit compares a value outputted from the CDR circuit with an expected value and outputs a comparison result.

Claims

1. A receiver circuit comprising:

a clock data recovery circuit;

a jitter generator unit configured to generate jitter having first characteristics;

a test pattern generator unit configured to generate a test pattern to which the jitter is added and to supply the test pattern to the clock data recovery circuit; and

a comparator unit configured to compare a value outputted from the clock data recovery circuit on the basis of the test pattern with an expected value and to output a comparison result.

2. The receiver circuit according to claim 1, wherein the first characteristics are a frequency and an amplitude of the jitter.

3. The receiver circuit according to claim 2 further comprising:

a jitter extractor unit configured to extract jitter from a clock recovered by the clock data recovery circuit; and

a jitter characteristic detector unit configured to detect a frequency and an amplitude of the extracted jitter.

4. A semiconductor integrated circuit comprising:

an internal circuit; and

a receiver circuit including;

a clock data recovery circuit configured to recover data and a clock from a received signal and to supply the data and the clock to the internal circuit;

a jitter generator unit configured to generate jitter having first characteristics;

a test pattern generator unit configured to generate a test pattern to which the jitter is added and to supply the test pattern to the clock data recovery circuit; and

a comparator unit configured to compare a value outputted from the clock data recovery circuit on the basis of the test pattern with an expected value and to output a comparison result.

5. The semiconductor integrated circuit according to claim 4, wherein the first characteristics are a frequency and an amplitude of the jitter.

6. The semiconductor integrated circuit according to claim 5, wherein the receiver circuit further including:

a jitter extractor unit configured to extract jitter from a clock recovered by the clock data recovery circuit; and

a jitter characteristic detector unit configured to detect a frequency and an amplitude of the extracted jitter.

7. A test method comprising:

generating jitter having first characteristics in a receiver circuit including a clock data recovery circuit;

generating a test pattern to which the jitter is added and supplying the test pattern to the clock data recovery circuit; and

comparing a value outputted from the clock data recovery circuit with an expected value and outputting a comparison result.

8. The test method according to claim 7, wherein the first characteristics are a frequency and an amplitude of the jitter.

9. The test method according to claim 8 further comprising:

extracting jitter from a clock recovered by the clock data recovery circuit; and

detecting a frequency and an amplitude of the extracted jitter.