EYE WIDTH MEASUREMENT AND MARGINING IN COMMUNICATION SYSTEMS

• US 20140270030A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Amir Laufer, Itamar Levin, Noam Familia, Vadim Levin
• Inventors: HAMMAD, DIMA, LEVIN, VADIM, LAUFER, AMIR, BAR-LEV, RON, FAMILIA, NOAM, LEVIN, ITAMAR
• Granted Patent: US 8,989,329 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 1/24 Testing correct operation
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0079 Receiver details

Abstract

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Claims

1. An apparatus comprising:

a controller module configured to decouple a phase detector from a loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal at a receiver clock signal frequency, the margining clock signal generated by an oscillator coupled to the loop filter;

a margining input module configured to apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input;

a compare module configured to compare a first bit stream and a second bit stream, the comparing configured to detect an error, the first bit stream related to a transmitted bit stream received by the receiver under test; and

a counter logic module configured to count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when an error is detected.

2. The apparatus of claim 1, further comprising a pseudo-random bit sequence (PRBS) generator configured to generate a pseudo-random bit sequence synchronized to the margining clock signal.

3. The apparatus of claim 2, wherein the first bit stream corresponds to a receiver bit stream and the second bit stream corresponds to the pseudo-random bit sequence.

4. The apparatus of claim 1, wherein the first bit stream is a receiver bit stream and the second bit stream is related to the first bit stream.

5. The apparatus of claim 1, wherein the margining input corresponds to a voltage and the oscillator is a voltage controlled oscillator.

6. The apparatus of claim 1, wherein the margining input corresponds to a digital value and the oscillator is a digital controlled oscillator.

7. A method comprising:

decoupling a phase detector from a loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal at a receiver clock signal frequency;

applying a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input;

comparing a first bit stream and a second bit stream, the first bit stream related to a transmitted bit stream received by the receiver under test, the comparing configured to detect an error; and

counting cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

8. The method of claim 7, further comprising generating a pseudo-random bit sequence synchronized to the margining clock signal.

9. The method of claim 7, further comprising generating the first bit stream based, at least in part, on the margining clock signal.

10. The method of claim 7, further comprising:

removing the margining input from the loop filter;

recoupling the phase detector and the loop filter;

delaying for a time interval configured to allow the margining clock signal and the receiver clock signal to synchronize; and

halting the test if the margining clock signal and the receiver clock signal are not synchronized at the end of the time interval.

11. The method of claim 7, further comprising:

removing the margining input from the loop filter after a time interval, the time interval corresponding to a phase shift between the receiver clock signal and the margining clock signal; and

dwelling at the phase shift for a number M of clock cycles while comparing and counting.

12. The method of claim 7, wherein the first bit stream is a receiver bit stream and the second bit stream is related to the first bit stream.

13. The method of claim 8, wherein the first bit stream corresponds to a receiver bit stream and the second bit stream corresponds to the pseudo-random bit sequence.

14. A receiver comprising:

a clock and data recovery (CDR) module comprising a phase detector, a loop filter coupled to an output of the phase detector, and an oscillator coupled to an output of the loop filter, the oscillator configured to generate a margining clock signal;

a data slicer module configured to receive the margining clock signal from the CDR module, to generate a first bit stream based, at least in part, on the margining clock signal and to provide a receiver clock signal to the CDR module, the first bit stream related to a transmitted bit stream received by the receiver; and

eye measurement circuitry comprising;

a controller module configured to decouple the phase detector from the loop filter in response to synchronizing the margining clock signal with the receiver clock signal at a receiver clock signal frequency;

a margining input module configured to apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input;

a compare module configured to compare the first bit stream and a second bit stream, the comparing configured to detect an error; and

a counter logic module configured to count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

15. The receiver of claim 14, wherein the data slicer module comprises a data slicer configured to provide a receiver bit stream.

16. The receiver of claim 14, wherein the data slicer module comprises a monitor slicer configured to provide a monitor bit stream, the monitor bit stream related to a monitor slicer reference voltage configured to facilitate measuring the eye width at an amplitude corresponding to the monitor slicer reference voltage.

17. The receiver of claim 15, wherein the data slicer module comprises a monitor slicer configured to provide the second bit stream, the second bit stream related to a monitor slicer reference voltage.

18. The receiver of claim 14, wherein the eye measurement circuitry further comprises a pseudo-random bit sequence (PRBS) generator configured to generate a pseudo-random bit sequence synchronized to the margining clock signal.

19. The receiver of claim 18, further comprising a decision feedback equalizer coupled to the data slicer module and configured to receive the pseudo-random bit sequence.

20. The receiver of claim 14, wherein the oscillator is a voltage controlled oscillator or a digital controlled oscillator.