Vertical Doping and Capacitive Balancing for Power Semiconductor Devices

• US 20140273374A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph, Stokes, Richard, Sapp, Steven, Deb Roy, Sukhendu
• Application Number:
  US13/842,694
• Publication Number:
  US 20140273374A1
• Time in Patent Office: Days
• US Class Current: 438/272
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.

Claims

1. A method for making semiconductor structure, comprising:

providing a semiconductor substrate;

providing an epitaxial layer on the substrate, the epitaxial layer comprising;

a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and

an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration;

providing a trench in the epitaxial layer;

forming a transistor structure in the trench; and

forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.

2. The method of claim 1, wherein the transistor structure comprises a shielded gate MOSFET device.

3. The method of claim 1, wherein the upper portion of the epitaxial layer extends to just below the well region.

4. The method of claim 1, wherein the first dopant concentration ranges from about 5×

10¹⁵ atoms/cm³ to about 3×

10¹⁷ atoms/cm³.

5. The method of claim 1, wherein the second dopant concentration ranges from about 1×

10¹³ atoms/cm³ to about 1×

10¹⁶ atoms/cm³.

6. The method of claim 1, wherein the second dopant concentration is about 1×

10¹⁵ atoms/cm³.

7. The method of claim 2, wherein the second concentration in the upper portion of the epitaxial layer reduces and flattens the electric field near the junction with well region.

8. The method of claim 1, wherein the method creates a higher mesa drift doping between the trenches and achieves a lower on-resistance performance while maintaining a high breakdown voltage.

21. The method of claim 1, wherein the trench extends below the upper portion of the epitaxial layer.

22. The method of claim 21, wherein the trench extends into the substrate.

23. The method of claim 1, wherein the doping concentration of the upper portion decreases towards the surface of the substrate.

24. The method of claim 1, wherein the doping concentration of the bottom portion decreases towards the surface of the substrate.

25. The method of claim 1, wherein the bottom portion dopant concentration is higher than the upper portion dopant concentration and both the upper and bottom portions have a decreasing dopant concentration towards the surface of the substrate.

26. The method of claim 1, further comprising an intermediate portion located between the lower portion and the upper portion and the intermediate portion has an increasing dopant concentration toward the surface of the substrate.

27. The method of claim 1, wherein the minority carrier lifetime is reduced by introducing traps in the mesa drift region between the trenches

9. A method for making a power semiconductor device, comprising:

providing a semiconductor substrate;

providing an epitaxial layer on the substrate, the epitaxial layer comprising;

a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and

an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration;

providing a trench in the epitaxial layer;

forming a transistor structure in the trench; and

forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.

10. The method of claim 9, wherein the transistor structure comprises a shielded gate MOSFET device.

11. The method of claim 9, wherein the upper portion of the epitaxial layer extends to just below the well region.

12. The method of claim 9, wherein the first dopant concentration ranges from about 5×

10¹⁵ atoms/cm³ to about 3×

10¹⁷ atoms/cm³.

13. The method of claim 9, wherein the second dopant concentration ranges from about 1×

10¹³ atoms/cm³ to about 1×

10¹⁶ atoms/cm³.

14. The method of claim 9, wherein the second dopant concentration is about 1×

10¹⁵ atoms/cm³.

15. The method of claim 10, wherein the second concentration in the upper portion of the epitaxial layer reduces and flattens the electric field near the junction with well region.

16. The method of claim 9, wherein the method creates a higher mesa drift doping between the trenches and achieves a lower on-resistance performance while maintaining a high breakdown voltage.

17. A method for making a shielded gate MOSFET device, comprising:

providing a semiconductor substrate;

providing an epitaxial layer on the substrate, the epitaxial layer comprising;

a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and

an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration;

providing a trench in the epitaxial layer;

forming an insulating layer on the bottom and sidewalls of the trench;

forming a conductive shield on the insulating layer;

forming an interlevel dielectric layer on the conductive shield;

forming a gate on the interlevel dielectric layer;

forming an insulation cap on the gate; and

forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.

18. The method of claim 17, wherein the first dopant concentration ranges from about 5×

10¹⁵ atoms/cm³ to about 3×

10¹⁷ atoms/cm³.

19. The method of claim 17, wherein the second dopant concentration ranges from about 1×

10¹³ atoms/cm³ to about 1×

10¹⁶ atoms/cm³.

20. The method of claim 17, wherein the second dopant concentration is about 1×

10¹⁵ atoms/cm³.