NEURAL SENSING DEVICE AND METHOD FOR MAKING THE SAME

• US 20140275911A1
• Filed: 03/13/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Kuo-Hua
• Granted Patent: US 9,089,268 B2
• Time in Patent Office: Days
• US Class Current: 600/372
• CPC Class Codes: A61B 2562/046 in a matrix array
• CPC Class Codes: A61B 2562/12 Manufacturing methods specially adapted for producing sensors for in-vivo measurements
• CPC Class Codes: A61B 5/24 Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
• CPC Class Codes: A61B 5/291 for electroencephalography [EEG]
• CPC Class Codes: A61B 5/685 Microneedles
• CPC Class Codes: A61B 5/6868 Brain
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68304 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/05569 : the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion and a plurality of microprobes. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The conductive vias are disposed in the microprobes and electrically connected to the integrated circuit portion.

Claims

1. A neural sensing device, comprising:

a base having an active surface and a backside surface;

an integrated circuit portion disposed on the active surface of the base; and

a plurality of microprobes protruding from the backside surface of the base, each of the microprobes having a conductive via disposed therein and electrically connected to the integrated circuit portion.

2. The neural sensing device of claim 1, wherein the conductive via penetrates through the base and the microprobe, extending from the active surface of the base to a tip of the microprobe.

3. The neural sensing device of claim 1, wherein a circular insulation material surrounds conductive metal of the conductive via.

4. The neural sensing device of claim 1, wherein the conductive vias are electrically isolated from each other.

5. The neural sensing device of claim 1, wherein the integrated circuit portion comprises at least one electrical element, a plurality of metal layers and at least one dielectric layer, the at least one electrical element is disposed adjacent to the active surface of the base and covered by the dielectric layer, and the metal layers are embedded in the dielectric layer.

6. The neural sensing device of claim 1, wherein each of the microprobes has a probe body and an isolation layer, wherein the probe body protrudes from the backside surface of the base, the conductive via penetrates through the probe body, and the isolation layer covers the probe body and has an opening to expose a tip of the conductive via.

7. The neural sensing device of claim 6, wherein the exposed tip is plated with platinum.

8. A neural sensing device, comprising:

a base having an active surface and a backside surface;

an integrated circuit portion disposed on the active surface of the base; and

a plurality of microprobes, wherein each of the microprobes has a probe body, an isolation layer and a conductive via, wherein the probe body protrudes from the backside surface of the base, the conductive via is disposed in the probe body, and the isolation layer covers the probe body and has an opening to expose a plated tip of the conductive via.

9. The neural sensing device of claim 8, wherein the microprobes can be used to penetrate the stratum germinativum layer of human skin to collect bio-signals via the exposed tips of the conductive vias.

10. The neural sensing device of claim 9, wherein, when the microprobes penetrate the stratum germinativum layer, the microprobes are electrically insulated from the stratum corneum layer of the skin by the isolation layer.

11. The neural sensing device of claim 8, further comprising:

a plurality of redistribution layers electrically connecting the integrated circuit portion and the conductive via;

at least one protection layer covering the redistribution layers; and

a plurality of under bump metallurgies (UBMs) disposed on the protection layer and electrically connected to the redistribution layers.

12. The neural sensing device of claim 11, wherein a tip of each of the conductive vias is exposed from the active surface of the base, and each of the redistribution layers contacts the exposed tip of each of the conductive vias.

13. The neural sensing device of claim 11, wherein the integrated circuit portion comprises a plurality of bottommost pads disposed on the active surface of the base, wherein a tip of each of the conductive vias is exposed from the active surface of the base, and each of the bottommost pads contacts the exposed tip of each of the conductive vias.

14. The neural sensing device of claim 8, wherein the base and the probe body are made of the same semiconductor material.

15. A method for making a neural sensing device, comprising:

(a) providing a wafer having a base and an integrated circuit portion disposed on an active surface of the base;

(b) forming a plurality of conductive vias in the base from the active surface of the base, wherein the conductive vias are electrically connected to the integrated circuit portion;

(c) thinning the base from a backside surface thereof to expose the conductive via;

(d) selectively removing the base from a backside surface thereof to form a plurality of probe bodies, wherein each of the conductive vias is disposed in each of the probes; and

(e) dicing the wafer to form a plurality of neural sensing devices.

16. The method of claim 15, wherein the step (b) comprises:

(b1) forming a plurality of openings on the integrated circuit portion to expose the active surface of the base;

(b2) forming the conductive via in the base from the active surface of the base according to the openings of the integrated circuit portion; and

(b3) forming a plurality of redistribution layers to electrically connect the integrated circuit portion and the conductive vias.

17. The method of claim 16, wherein in step (b3), the redistribution layers extend into the openings of the integrated circuit portion to contact the conductive vias.

18. The method of claim 16, wherein the step (b2) comprises:

(b21) forming a plurality of holes on the active surface of the base;

(b22) forming a circular insulation material on a sidewall of each of the holes so as to define a central hole; and

(b23) filling an conductive metal in the central hole.

19. The method of claim 16, wherein after step (b3), the method further comprises:

(b4) forming at least one protection layer to cover the redistribution layers; and

(b5) forming a plurality of under bump metallurgies (UBMs) on the protection layer to electrically connect the redistribution layers.

20. The method of claim 15, wherein after step (d), the method further comprises:

(d1) forming an isolation layer on the probe bodies and the backside surface of the base, wherein the isolation layer has a plurality of openings to expose the conductive vias; and

(d2) forming a plurality of tip metals in the openings of the isolation layer to contact the conductive vias.