Namespace Access Control in NVM Express PCIe NVM with SR-IOV

• US 20140281040A1
• Filed: 05/22/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Liu, Jinshui
• Granted Patent: US 9,003,071 B2
• Time in Patent Office: Days
• US Class Current: 710/3
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

A method implemented by a non-volatile memory (NVM) controller comprising obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function, determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space, and accessing the namespace based on the mapping between the PCIe function and the namespace.

Claims

1. A method implemented by a non-volatile memory (NVM) controller comprising:

obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function;

determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space; and

accessing the namespace based on the mapping between the PCIe function and the namespace.

2. The method of claim 1, wherein the NSID is a first NSID, and wherein determining the mapping between the PCIe function and the namespace comprises:

obtaining a second NSID by reading the data structure; and

determining a match between the first and second NSIDs.

3. The method of claim 2, wherein the PCIe function is one of a plurality of PCIe functions coupled to the NVM controller and comprising a physical function (PF) and a number of virtual functions (VFs), wherein the data structure is a shared namespace register (SNSR) comprising the second NSID, and wherein a second namespace identified by the second NSID is sharable by all of the PCIe functions through the NVM controller.

4. The method of claim 3, wherein the SNSR further comprises a validity bit, wherein determining the mapping between the PCIe function and the namespace further comprises checking the validity bit.

5. The method of claim 3, wherein determining the mapping between the PCIe function and the namespace further comprises, upon failure of determining the match between the first and second NSIDs:

generating an entry index based on the PCIe function;

locating an entry among a plurality of entries in a namespaces access control (NSAC) table based on the generated entry index;

obtaining a third NSID from the located entry; and

determining a match between the first and third NSIDs.

6. The method of claim 5, further comprising initializing and configuring the SNSR and the NSAC table using a virtual machine manager (VMM) before executing any NVMe command from a corresponding PCIe function, wherein the SNSR and NSAC table are readable by the NVM controller but not configurable by the NVM controller.

7. The method of claim 2, wherein the data structure comprises a plurality of entries, wherein determining the mapping between the PCIe function and the namespace further comprises:

generating an entry index based on the PCIe function; and

locating an entry among the plurality of entries using the generated entry index as an address to the data structure,

and wherein the second NSID is obtained from the located entry.

8. The method of claim 7, wherein the located entry comprises a validity bit, wherein determining the mapping between the PCIe function and the namespace further comprises checking the validity bit.

9. The method of claim 7, wherein the PCIe function is one of a plurality of PCIe functions coupled to the NVM controller and comprising a physical function (PF) and a number of virtual functions (VFs), and wherein the memory address space belongs to the PF.

10. The method of claim 2, wherein the data structure comprises a plurality of entries, wherein determining the mapping between the PCIe function and the namespace further comprises, prior to obtaining the second NSID:

generating an entry index by computing a hash function of the first NSID; and

locating an entry among the plurality of entries using the generated entry index as an address to the data structure,

and wherein the second NSID is obtained from the located entry.

11. The method of claim 10, wherein determining the mapping between the PCIe function and the namespace further comprises:

generating a PCIe function number based on the PCIe function;

locating a bit in the located entry using the generated PCIe function number; and

determining validity of the bit,

and wherein accessing the namespace identified by the second NSID occurs only when the bit is determined to be valid.

12. The method of claim 1, wherein the data structure comprises a plurality of entries, wherein determining the mapping between the PCIe function and the namespace comprises:

locating an entry among the plurality of entries using low order bits of the NSID as an index of the data structure;

checking a validity bit of the located entry;

generating a PCIe function number based on the PCIe function;

locating a bit in the located entry using the generated PCIe function number; and

determining validity of the bit,

and wherein accessing the namespace occurs only when the bit is determined to be valid and the validity bit of the located entry is valid.

13. An apparatus comprising:

one or more non-volatile memory (NVM) devices having a total storage capacity represented by a plurality of namespaces;

a NVM express (NVMe) peripheral component interconnect express (PCIe)-NVM (NVMe PCIe-NVM) controller coupled to the NVM devices; and

a plurality of PCIe functions including a physical function (PF) and a number of virtual functions (VF) coupled to the NVMe PCIe-NVM controller,

wherein the NVMe PCIe-NVM controller is configured to;

getting a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a PCIe function of the PCIe functions;

determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a memory address space of the PF; and

accessing the namespace based on the mapping between the PCIe function and the namespace.

14. The apparatus of claim 13, further comprising:

a plurality of virtual machines (VMs); and

a VM manager (VMM) configured to, prior to the NVMe PCIe-NVM controller getting the NVMe command;

assign a VF in the number of VFs to one of the VMs; and

configure the data structure to establish the mapping between the PCIe function and the namespace,

wherein the data structure is readable by the NVMe PCIe-NVM controller but not configurable by the NVMe PCIe-NVM controller.

15. The apparatus of claim 13, wherein the NSID is a first NSID, wherein the data structure is a shared namespace register (SNSR) comprising a second NSID, wherein a second namespace identified by the second NSID is sharable by all of the PCIe functions through the NVMe PCIe-NVM controller, and wherein determining the mapping between the PCIe function and the namespace comprises determining a match between the first and second NSIDs.

16. The apparatus of claim 13, wherein the data structure comprises a plurality of entries, wherein determining the mapping between the PCIe function and the namespace further comprises:

generating an entry index based on the PCIe function;

locating an entry among the plurality of entries using the generated entry index as an address to the data structure;

obtaining a second NSID from the located entry; and

determining a match between the first and second NSIDs.

17. A method implemented in a computer system comprising:

dividing a storage capacity of one or more non-volatile memory (NVM) devices into a plurality of namespaces; and

allocating a namespace in the plurality of namespaces to at least one peripheral component interconnect express (PCIe) function such that only the allocated namespace is accessible to the at least one PCIe function, wherein the at least one PCIe function belongs to a plurality of PCIe functions present in the computer system comprising a physical function (PF) and a number of virtual functions (VFs).

18. The method of claim 17, further comprising:

assigning the at least one PCIe function to one or more virtual machines (VMs) using a VM manager (VMM); and

communicating data between the VMs and the allocated namespace through the at least one PCIe function and bypassing the VMM.

19. The method of claim 18, wherein allocating the namespace comprises configuring a shared namespace register (SNSR), or a namespaces access control (NSAC) table, or both, using the VMM.

20. The method of claim 19, wherein communicating data between the VMs and the allocated namespace comprises:

getting a NVM express (NVMe) command comprising a namespace identifier (NSID) via one of the PCIe functions by a NVM controller coupled to the PCIe function;

determining a mapping between the PCIe function and the namespace identified by the NSID based on allocation of the namespace; and

executing the NVMe command to access the namespace based on the mapping.