METHODS AND APPARATUS FOR MULTI-DROP DIGITAL BUS

• US 20140281076A1
• Filed: 03/17/2014
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hollabaugh, James, Breece, David III, Kalinichev, Kirill
• Granted Patent: US 10,102,175 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

Apparatus and methods for digital bus operation. In one embodiment, the digital bus is a bidirectional, time-division multiplexing (TDM) audio bus operation, and a bus technology is described that enables multi-drop (e.g., multiple device, multiple node, etc.) connectivity for real-time audio over a small form factor interface (e.g., as few as two (2) wires). Specifically, an exemplary tri-level signaling scheme provides bidirectional functionality, real-time clock edges, audio data, in a multi-drop topology in one implementation.

Claims

1. A digital bus architecture, comprising:

a time-division multiplexing (TDM) signaling protocol configured to transmit a clock signal comprising real-time digital data, the clock signal configured to enable multi-drop connectivity for the real-time digital data over an interface.

2. The architecture of claim 1, further comprising a tri-level signaling scheme configured to enable a first bus node to provide clock signal to one or more other bus nodes, and/or receive clock signal from any of the other bus nodes.

3. The architecture of claim 2, wherein the real time digital data comprises digital audio data having one or more quality of service requirements associated therewith.

4. The architecture of claim 2, wherein a data value of the real-time digital data is derived from a clock cycle of the clock signal.

5. The architecture of claim 2, wherein a data value of the real-time digital data at a time slot of the clock signal is indicated by a direction of an edge transition of the clock signal at the time slot.

6. The architecture of claim 2, wherein a data value of the real-time digital data at a time slot of the clock signal is indicated by a voltage level of the clock signal at the time slot.

7. The architecture of claim 2, wherein signaling of the tri-level signaling scheme is selected from a group consisting of:

(i) single-ended signaling and (ii) differential signaling.

8. A method of operating a digital audio network comprising one or more bus nodes, wherein each node comprises one or more audio sources and/or audio sinks, the method comprising:

arbitrating for control of the audio network;

receiving audio data to be transmitted to at least one of the one or more bus nodes; and

transmitting a real-time clock with edge transitions and logic levels;

wherein the real-time clock is configured based at least on the received audio data.

9. The method of claim 8, wherein the transmitting of the real-time clock is configured to be transmitted to any of the bus nodes of the network.

10. The method of claim 8, wherein an edge transition of a clock cycle of the real-time clock is configured based at least on a data value of the received audio data associated with the respective clock cycle.

11. The method of claim 8, wherein a logic level of a clock cycle of the real-time clock is configured based at least on a data value of the received audio data associated with the respective clock cycle.

12. The method of claim 8, wherein the act of transmitting is based at least on a tri-level signaling scheme.

13. The method of claim 8, wherein the act of transmitting further comprises transmitting control data over a bidirectional link and transmitting the real-time clock over a unidirectional link.

14. The method of claim 8, wherein the act of arbitrating comprises allocating one or more time slots to at least one bus node for the transmitting.

15. The method of claim 14, wherein the real-time clock is further configured based at least on the allocated one or more time slots.

16. A simplified digital data interface, comprising:

a two-wire signaling conductor interface; and

logic configured to implement a time-divided transmission protocol over the conductor interface so as to enable single-ended signaling for the reception of digital audio data.

17. The simplified digital data interface of claim 16, wherein:

the digital audio data is transmitted in the form of a clock signal comprising a plurality of clock cycles; and

the logic is further configured to derive a data value of the digital audio data associated with a respective clock cycle of the clock signal.

18. The simplified digital data interface of claim 17, wherein the data value is derived based on at least a logic level of the respective clock cycle.

19. The simplified digital data interface of claim 17, wherein the data value is derived based on at least an edge direction of an edge transition of the clock cycle.

20. The simplified digital data interface of claim 17, wherein:

the simplified digital data interface is assigned one or more time slots of the clock signal; and

data values are only derived from the clock signal for the cycles that correspond with the assigned one or more time slots.