ATOMIC WRITE COMMAND SUPPORT IN A SOLID STATE DRIVE

• US 20140281145A1
• Filed: 05/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: TOMLIN, ANDREW J., JONES, JUSTIN, MULLENDORE, RODNEY N.
• Granted Patent: US 9,218,279 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.

Claims

1. A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices that are configured to store a plurality of physical pages, the method comprising:

storing data in a plurality of logical pages (L-Pages), each of the plurality of L-Pages being associated with a logical address;

maintaining a logical-to-physical address translation map in the volatile memory, the translation map being configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address;

receiving the atomic write command;

storing data specified by the atomic write command in at least one L-Page; and

deferring an update to at least one entry in the translation map associated with the at least one L-Page storing the data specified by the atomic write command until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.

2. The method of claim 1, wherein storing data specified by the atomic write command comprises:

storing, in the volatile memory, mapping information related to the atomic write command, the mapping information including an indication of the physical location of each L-Page storing the data specified by the atomic write command.

3. The method of claim 2, further comprising:

after all L-Pages storing the data specified by the atomic write command are written, updating the at least one entry in the translation map associated with the at least one L-Page with the indication of the physical location.

4. The method of claim 3, further comprising:

acknowledging a completion of the atomic write command to a host coupled to the data storage device after the translation map has been updated.

5. The method of claim 2, wherein the translation map is configured to store mapping entries spanning at least a portion of a logical capacity of the data storage device and wherein the mapping information for the atomic write command includes one or more logical addresses that extend beyond the logical capacity of the data storage device.

6. The method of claim 2, wherein the mapping information for the atomic write command is stored separately from the translation map.

7. The method of claim 2, further comprising:

maintaining, in the plurality of non-volatile memory devices, a plurality of system journals (S-Journals) defining physical-to-logical address correspondences, each journal comprising a plurality of system journal entries, each entry being configured to associate one or more physical pages to each L-Page; and

wherein storing data specified by the atomic write command further comprises;

generating an S-Journal entry for each of the at least one L-Page storing data specified by the atomic write command, the generated S-Journal entry being configured to enable a determination of whether the atomic write command was completed or not completed upon reconstruction of the translation map.

8. The method of claim 7, wherein each S-Journal entry for the atomic write command comprises one of a plurality of unique sequence numbers and an indication of a physical location, within the non-volatile memory devices, of one L-Page storing data specified by the atomic write command.

9. The method of claim 8, further comprising writing the sequence number and the indication of physical location that is part of the S-Journal entry in a header associated with the one L-Page.

10. The method of claim 8, further comprising generating the unique sequence number, wherein each sequence number generated is configured to be non-repeating.

11. The method of claim 8, further comprising providing a plurality of slots in a power-safe temporary storage, each slot being configured to store one of the plurality of unique sequence numbers.

12. The method of claim 11, wherein each slot is not used for consecutive sequence numbers.

13. The method of claim 11, further comprising:

saving a unique sequence number for a current or next atomic write command in the power-safe temporary storage.

14. The method of claim 13, further comprising one of changing, in the power-safe temporary storage, the unique sequence number associated with the atomic write command after the atomic write command is completed and before acknowledging the completion of the atomic write command to a host coupled to the data storage device.

15. The method of claim 13, further comprising determining whether an atomic write command has completed during reconstruction of the translation map by comparing the unique sequence number stored in the S-Journal entry with the unique sequence number stored in the power-safe temporary storage.

16. The method of claim 15, wherein a match between the unique sequence number stored in the S-Journal entry and the unique sequence number stored in the power-safe temporary storage indicates an incomplete atomic write command.

17. The method of claim 11, wherein the power-safe temporary storage comprises one of a magnetic random access memory (MRAM), a battery-backed random access memory and a non-volatile random access memory (NVRAM).

18. The method of claim 1, further comprising:

deferring free space accounting until after all L-Pages storing data specified by the atomic write command have been stored in the non-volatile memory devices and the atomic write command is determined to have completed.

19. The method of claim 1, further comprising:

receiving a non-atomic write command;

storing data specified by the non-atomic write command in at least one L-Page; and

updating the translation map after each L-Page storing data specified by the non-atomic write command data is written.

20. The method of claim 1, further comprising:

storing information tracking a range of L-Pages in which the writing of at least some L-Pages specified by the atomic write command have been completed;

in the event the atomic write command does not complete, at reconstruction;

using the stored tracking information to generate a copy command that copies a current version of L-Pages within the range that existed before the atomic write command.

21. A data storage device controller, comprising:

a processor, the processor being configured to perform an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices that are configured to store a plurality of physical pages, by at least;

storing data in a plurality of logical pages (L-Pages), each of the plurality of L-Pages being associated with a logical address;

maintaining a logical-to-physical address translation map in the volatile memory, the translation map being configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address;

receiving the atomic write command;

storing data specified by the atomic write command in at least one L-Page; and

deferring an update to at least one entry in the translation map associated with the at least one L-Page storing the data specified by the atomic write command until all L-Pages storing data specified by the atomic write command have been written in in a power-safe manner.

22. The data storage device controller of claim 21, wherein storing data specified by the atomic write command comprises:

storing, in the volatile memory, mapping information related to the atomic write command, the mapping information including an indication of the physical location of each L-Page storing the data specified by the atomic write command.

23. The data storage device controller of claim 22, wherein the processor is further configured to, after all L-Pages storing the data specified by the atomic write command are written, update the at least one entry in the translation map associated with the at least one L-Page with the indication of the physical location.

24. The data storage device controller of claim 23, wherein the processor is further configured to acknowledge a completion of the atomic write command to a host coupled to the data storage device after the translation map has been updated.

25. The data storage device controller of claim 22, wherein the translation map is configured to store mapping entries spanning at least a portion of a logical capacity of the data storage device and wherein the mapping information for the atomic write command includes one or more logical addresses that extend beyond the logical capacity of the data storage device.

26. The data storage device controller of claim 22, wherein the mapping information for the atomic write command is stored separately from the translation map.

27. The data storage device controller of claim 22, wherein the processor is further configured to maintain, in the plurality of non-volatile memory devices, a plurality of system journals (S-Journals) defining physical-to-logical address correspondences, each journal comprising a plurality of system journal entries, each entry being configured to associate one or more physical pages to each L-Page;

and

wherein storing data specified by the atomic write command further comprises;

generating an S-Journal entry for each of the at least one L-Page storing data specified by the atomic write command, the generated S-Journal entry being configured to enable a determination of whether the atomic write command was completed or not completed upon reconstruction of the translation map.

28. The data storage device controller of claim 27, wherein each S-Journal entry for the atomic write command comprises one of a plurality of unique sequence numbers and an indication of a physical location, within the non-volatile memory devices, of one L-Page storing data specified by the atomic write command.

29. The data storage device controller of claim 28, wherein the processor is further configured to write the sequence number and the indication of physical location that is part of the S-Journal entry in a header associated with the one L-Page.

30. The data storage device controller of claim 28, wherein the processor is further configured to generate the unique sequence number, wherein each sequence number generated is configured to be non-repeating.

31. The data storage device controller of claim 28, wherein the processor is further configured to provide a plurality of slots in a power-safe temporary storage, each slot being configured to store one of the plurality of unique sequence numbers.

32. The data storage device controller of claim 31, wherein each slot is not used for consecutive sequence numbers.

33. The data storage device controller of claim 31, wherein the processor is further configured to save a unique sequence number for a current or next atomic write command in the power-safe temporary storage.

34. The data storage device controller of claim 33, wherein the processor is further configured to change, in power-safe temporary storage, the unique sequence number associated with the atomic write command after the atomic write command is completed and before acknowledging the completion of the atomic write command to a host coupled to the data storage device.

35. The data storage device controller of claim 33, wherein the processor is further configured to determine whether an atomic write command has completed during reconstruction of the translation map by comparing the unique sequence number stored in the S-Journal entry with the unique sequence number stored in the power-safe temporary storage.

36. The data storage device controller of claim 35, wherein a match between the unique sequence number stored in the S-Journal entry and the unique sequence number stored in the power-safe temporary storage indicates an incomplete atomic write command.

37. The data storage device controller of claim 31, wherein the power-safe temporary storage comprises one of a magnetic random access memory (MRAM), a battery-backed random access memory and a non-volatile random access memory (NVRAM).

38. The data storage device controller of claim 21, wherein the processor is further configured to defer free space accounting until after all L-Pages storing data specified by the atomic write command have been stored in the non-volatile memory devices and the atomic write command is determined to have completed.

39. The data storage device controller of claim 21, wherein the processor is further configured to:

receive a non-atomic write command;

store data specified by the non-atomic write command in at least one L-Page; and

update the translation map after each L-Page storing data specified by the non-atomic write command data is written.

40. The data storage device controller of claim 21, wherein the processor is further configured to:

store information tracking a range of L-Pages in which the writing of at least some L-Pages specified by the atomic write command have been completed;

in the event the atomic write command does not complete, at reconstruction;

use the stored tracking information to generate a copy command that copies a current version of L-Pages within the range that existed before the atomic write command.

41. A data storage device, comprising:

the volatile memory;

the plurality of non-volatile memory devices; and

the data storage device controller of claim 21.