APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY

• US 20140281149A1
• Filed: 06/06/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas, Walker, Robert, Roberts, David A.
• Granted Patent: US 10,042,750 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

Claims

1. An apparatus, comprising:

a processing unit configured to run an operating system;

a memory coupled to the processing unit, the memory configured to communicate with the processing unit via a memory bus; and

an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit, wherein the adaptive memory controller is configured to manage the memory based on the monitored statistical data.

2. The apparatus of claim 1, wherein the operating system is a memory hypervisor (MMH) operating system, wherein the MMH operating system provides memory management threads (MMT) configured to manage the memory, wherein the MMH operating system is configured to support a guest operating system run on the processing unit.

3. The apparatus of claim 2, wherein the adaptive memory controller comprises a memory management processor (MMP) configured to run the MMT, wherein the MMP running the MMT is configured to manage the memory based on the monitored statistical data.

4. The apparatus of claim 3, wherein the MMP comprises a cache and a direct-memory access (DMA) engine, wherein the DMA engine is configured communicate with the memory.

5. The apparatus of claim 4, wherein the processing unit includes a cache and the cache of the MMP is coupled to the cache of the processing unit via a common bus.

6. The apparatus of claim 3, wherein the processing unit is configured to execute the MMH operating system using a first instruction set, and wherein the MMP is configured to execute the MMH operating system using a second instruction set.

7. The apparatus of claim 3, wherein the memory comprises a memory controller and at least one of non-volatile memory or volatile memory.

8. The apparatus of claim 7, wherein the at least one of the non-volatile memory or the volatile memory is a multi-channel memory.

9. The apparatus of claim 7, wherein the MMP running the MMT being configured to manage the memory comprises the MMP running the MMT being configured to at least one of:

change a frequency of a portion of the at least one of the non-volatile memory or the volatile memory;

change a refresh period of a portion of the volatile memory;

perform a memory scrub of a portion of the at least one of the non-volatile memory or the volatile memory;

change a multi-level cell mode of a portion of the at least one of the non-volatile memory or the volatile memory;

or

change address mapping of a portion of the at least one of the non-volatile memory or the volatile memory.

10. The apparatus of claim 3, wherein the MMP running the MMT being configured to manage the memory comprises the MMP running the MMT being configured to manage migration of information in the memory.

11. The apparatus of claim 10, wherein the MMP running the MMT being configured to manage migration of information comprises the MMP running the MMT being configured to provide memory commands to a memory controller instructing the memory controller to move blocks of information in the memory.

12. The apparatus of claim 3, wherein the MMP is configured to run the MMT to determine when to reconfigure the memory based on the monitored statistical data.

13. The apparatus of claim 3, wherein the MMP is configured to run the MMT to determine how to reconfigure the memory based on monitored statistical data.

14. The apparatus of claim 3, wherein the MMP is configured to run the MMT to map information using an intermediate information depth map

15. The apparatus of claim 1, wherein the adaptive memory controller further comprises a performance management unit (PMU) configured to monitor the monitored statistical data, the PMU further comprising a PMU interface configured to couple the PMU to the processing unit and the MMP via a common bus and to a memory controller of the memory.

16. The apparatus of claim 12, wherein the PMU interface is configured to couple the PMU to the memory controller via at least one of the memory bus or a direct connection.

17. The apparatus of claim 1, wherein the adaptive memory controller configured to manage the memory based on the monitored statistical data comprises the adaptive memory controller configured to manage information depth and location based on traffic between the processing unit and the memory 220.

18. The apparatus of claim 1, wherein the adaptive memory controller configured to manage the memory based on the monitored statistical data comprises the adaptive memory controller configured to perform dynamic reconfiguration of the memory to match an information mapping with changing memory patterns of threads running on the processing unit.

19. An apparatus comprising:

a processing unit configured to run an operating system;

a memory coupled to the processing unit, the memory configured to communicate with the processing unit via a memory bus; and

a memory translation unit (MTU) configured to manage information migration stored at the memory, the MTU further configured to support an intermediate depth map of the memory during the migration of the information stored at the memory from a first depth map to a second depth map by maintaining mapping tables.

20. The apparatus of claim 19, wherein the MTU further comprises the mapping tables.

21. The apparatus of claim 19, wherein the MTU further comprises a cache having data of the mapping tables, and wherein the memory further comprises the mapping tables.

22. The apparatus of claim 19, wherein the MTU further comprises a configurations and command information unit configured to maintain and update configurations of the memory.

23. The apparatus of claim 22, wherein the configurations and command information unit configured to maintain and update configurations of the memory comprises maintaining and updating at least one of a frequency of the memory, a refresh period of the memory, a multi-level cell (MLC) mode of the memory, a memory channel address depth mapping, or a combination thereof.

24. An apparatus, comprising:

a memory configured to store information; and

a processing unit configured to run an operating system, the processing unit configured to manage information depth mapping of the memory, wherein responsive to a request to migrate information stored at memory of the memory from a first information depth map to a second information depth map, the processing unit configured to migrate the information stored at the memory of memory to an intermediate information depth map, wherein the first information depth map has a first information depth, wherein the second information depth map and the intermediate information depth map each have a second information depth.

25. The apparatus of claim 24, wherein the processing unit is further configured to initiate a scrubbing operation to transition to the second information depth map based on an event.

26. The apparatus of claim 24, further comprising a memory translation unit configured to manage address mapping during migration of the information stored at the memory of the memory from the first information depth map to the intermediate information depth map.

27. The apparatus of claim 24, wherein the first information depth map is a sequential depth map, and wherein the second information depth map and the intermediate information depth map are each one of a parallel depth map, a sequential depth map, or a combination thereof.

28. The apparatus of claim 24, wherein the processing unit is a memory management processing unit of an adaptive memory controller.

29. An apparatus, comprising:

a memory configured to store information, wherein memory of the memory is configured with two or more information depth maps; and

a memory translation unit (MTU) configured to support an intermediate depth map of the memory during the migration of the information stored at the memory from a first information depth map of the two or more information depth maps to a second information depth map of the two or more information depth by maintaining mapping tables, wherein the MTU is further configured to provide a mapped address associated with a requested address of a memory access request to the memory based on the mapping tables.

30. The apparatus of claim 29, wherein the mapping tables comprise at least one of an old depth map table, a new depth map table, or a region/sub-region table.

31. The apparatus of claim 29, wherein the MTU further comprises a comparator configured to provide a control signal having a value based on a comparison of data in the mapping tables, wherein the data in the mapping tables corresponds to a region of the memory that is associated with the logical address.

32. The apparatus of claim 31, wherein the MTU further comprises an address scrambler configured to translate the requested address to produce a translated requested address based on an address map.

33. The apparatus of claim 32, wherein the MTU further comprises a multiplexer configured to provide the mapped address based have that is selected from one of the requested address or the translated requested address based on a value of the control signals from the comparator.

34. A method, comprising:

retrieving information in memory responsive to memory access requests received from a processing unit; and

managing a configuration of the memory at a memory management processor (MMP) running a memory management (MMH) hypervisor operating system based on monitored statistical data associated with the memory and the processing unit.

35. The method of claim 34, further comprising receiving the monitored statistical data associated with the memory and the processing unit.

36. The method of claim 34, wherein the monitored statistical data associated with the memory comprises at least one of depth map setting of information stored at the memory, information mapping of and between portions of the memory, frequency of accesses of portions of the memory, or any combination thereof.

37. The method of claim 34, wherein the monitored statistical data associated with the processing unit comprises at least one of types of the memory access requests, frequency of the memory accesses, idle time of the processing unit, or any combination thereof.

38. The method of claim 34 wherein managing the configuration of the memory at the MMP running the MMH hypervisor operating system based on monitored statistical data associated with the memory and the processing unit comprises managing migration of information in the memory.

39. The method of claim 38, wherein managing migration of information in the memory comprises:

providing memory commands to the memory; and

moving blocks of information in the memory responsive to the memory commands.

40. The method of claim 38, wherein managing migration of information in the memory further comprises managing metadata of page tables and translation lookaside buffers.

41. The method of claim 34, wherein managing migration of information in the memory further comprises, responsive to receiving a memory access request for information stored in a portion of the memory undergoing a migration:

generating a page fault in the MMH operating system while the requested information is unavailable; and

providing the information when the portion of the memory become available.

42. The method of claim 40, wherein managing migration of information in the memory further comprises, responsive to receiving a memory access request for information stored in a portion of the memory undergoing a migration:

stalling a thread making the request in the MMH operating system while the requested information is unavailable; and

providing a translation of a logical address of the memory access request associated with a new address of the memory where the information is stored responsive to completion of movement of the information.

43. The method of claim 40, wherein managing metadata of page tables and translation lookaside buffers further comprises storing the metadata in shadow page tables and translation lookaside buffers that are not visible to a guest operating system.

44. The method of claim 34, wherein managing the configuration of the memory at the MMP running the MMH hypervisor operating system based on monitored statistical data associated with the memory and the processing unit comprises moving a portion of the memory from a first information depth map to an intermediate information depth map, wherein the intermediate information depth map is invisible to a processing unit running a guest operating system.

45. The method of claim 34, wherein responsive to receipt of a memory access request to the portion of memory mapped according to an intermediate information depth map from the processing unit:

performing an initial translation of a logical address of the memory access request at a memory translation unit to produce a translated address; and

translating the translated address into a physical address of the memory.

46. The method of claim 34, wherein managing the configuration of the memory at the MMP running the MMH hypervisor operating system based on monitored statistical data associated with the memory and the processing unit comprises at least one of:

changing a frequency of a portion of the memory;

changing a refresh period of a portion of the memory;

changing a multi-level cell mode of a portion of memory;

or

changing address mapping of a portion of the memory.

47. A method, comprising:

receiving, at a processing unit of a computing system, a request to move from a first information depth map to a second information depth map for a portion of a memory of the computing system, wherein the first information depth map has a first information depth and the second information depth map has a second information depth;

determining whether the computing system has sufficient resources to perform the move from the first information depth map to the second information depth map responsive to the request; and

providing commands from the processing unit to the memory to perform migration from the first information depth map to an intermediate information depth map for the portion of the memory based on a determination that the computing system has insufficient resources to perform the move from the first information depth map to the second information depth map, wherein the intermediate information depth map has the second information depth.

48. The method of claim 47, further comprising providing commands from the processing unit to the memory to perform a scrubbing operation to transition from the intermediate information depth map to the second information depth map responsive to an event.

49. The method of claim 48, wherein migrating from the first information depth map to the intermediate information depth map requires a first count of moves, and wherein migrating directly from the first information depth map to the second information depth map requires a second count of moves.

50. The method of claim 48, wherein the event comprises at least one of an idle memory, the computing system switched to a performance mode, the computing system is running a scrubbing operation on the portion of the memory, or combinations thereof.

51. The method of claim 47, wherein the determination that the computing system has insufficient resources to perform the move from the first information depth map to the second information depth map based on the computing system being in a power conservation mode.

52. A method, comprising:

receiving, at a memory translation unit, a memory access request, the memory access request including a requested address;

determining a mapping state of a region of a memory associated with the requested address; and

providing a mapped address to the memory, wherein the mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

53. The method of claim 52, wherein determining a mapping state of a region of a memory associated with the requested address comprises:

comparing an entry in an old depth map table associated with the region with an entry in a depth map table associated with the region; and

responsive to the entry of the old depth map table matching the entry of the depth map table, providing the requested address as the mapped address.

54. The method of claim 53, further comprising, responsive to the entry of the old depth map table being mismatched with the entry of the depth map table:

determining a state of the region from a region/sub-region table; and

responsive to the region/sub-region table indicating an intermediate mapped state;

providing the translated requested address as the mapped address.

55. The method of claim 52, further comprising, responsive to the region/sub-region table indicating a move is not in progress in the region, providing the requested address to the memory to be decoded using the old depth map table.

56. The method of claim 52, further comprising, responsive to the region/sub-region table indicating a move is complete in the region, providing the requested address to the memory to be decoded using the depth map table.