METHOD AND A SYSTEM TO VERIFY SHARED MEMORY INTEGRITY

• US 20140281195A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huynh, Duy Q., McKinney, Lyndsi R.
• Granted Patent: US 9,552,296 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache

Abstract

A method, a system and a computer program product including instructions for verification of the integrity of a shared memory using in line coding is provided. It involves an active step wherein multiple bus masters write a corresponding data to a shared memory. After that it also includes a verification step where data entered in the shared memory by multiple bus masters is verified.

Claims

1. A method for verifying an integrity of a shared memory using inline coding, the shared memory comprising a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the method comprising:

an active stage step, wherein the active stage step comprises;

writing by each of the plurality of bus masters, a corresponding data to at least one memory unit from the plurality of memory units;

updating status corresponding to the at least one memory unit in a status database to modified state; and

a verification stage step, wherein the verification stage step comprises;

reading back the corresponding data written by each of the plurality of bus masters, from the at least one memory unit;

comparing the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is a substantially similar to the corresponding data; and

updating and/or maintaining the status corresponding to the at least one memory unit in the status database to at least one of;

a verified state, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

the modified state, on the event of a mismatch between the data read back and the expected data written by at least one of the plurality of bus masters.

2. The method according to claim 1, wherein the plurality of bus masters is any one of a PPC440 PPC464, PPC476 and DMA.

3. The method according to claim 1, wherein the shared memory is any one of a DDR1, DDR2, DDR3 and SRAM memory.

4. The method according to claim 1, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256 or 512 bits.

5. The method according to claim 1, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide.

6. A system for verifying an integrity of a shared memory using inline coding, the shared memory comprising a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the system comprising:

a write module for writing by each of the plurality of bus masters, a corresponding data to at least one memory unit from the plurality of memory units;

a read module for reading back the corresponding data written by each of the plurality of bus masters, from the at least one memory unit;

a compare module for matching the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is substantially similar to the corresponding data; and

an update module to update and/or maintain status corresponding to the at least one memory unit in a status database, wherein the update module performs at least one of;

update the status corresponding to the at least one memory unit in the status database to modified state when the corresponding data is written by each of the plurality of bus masters;

update the status database for the at least one memory unit to verified, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

maintain the status database for the at least one memory unit to the modified state, on the event of a mismatch being found between the data read back and the expected data written, by at least one of the plurality of bus masters

7. The system according to claim 6, wherein the plurality of bus masters is any one of a PPC440PPC464, PPC476, and a DMA.

8. The system according to claim 6, wherein the shared memory is any one of a DDR1, DDR2 or a DDR3 memory.

9. The system according to claim 6, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256, or 512 bits.

10. The system according to claim 6, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide word.

11. A computer program product comprising computer readable medium, the computer readable medium comprising an inline code used for verifying an integrity of a shared memory, the shared memory comprises a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the computer program product comprising instructions for:

an active stage step, wherein the active stage step comprises;

writing by each of the plurality of bus masters, a corresponding data to at least one memory unit from the plurality of memory units;

updating status corresponding to the at least one memory unit in a status database to modified state; and

a verification stage step, wherein the verification stage step comprises;

reading back the corresponding data written by each of the plurality of bus masters, from the at least one memory unit;

comparing the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is substantially similar to the corresponding data; and

updating and/or maintaining the status corresponding to the at least one memory unit in the status database to at least one of;

a verified state, on the event of a match being found between the data read back and the corresponding data written, by at least one of the plurality of bus masters; and

the modified state, on the event of a mismatch between the data read back and the expected data written by at least one of the plurality of bus masters.

12. The computer program product of claim 11, wherein the plurality of bus masters is any one of a PPC440 PPC464, PPC476 and a DMA.

13. The computer program product of claim 11, wherein the shared memory is any one of a DDR1, a DDR2, a DDR3 and a SRAM memory.

14. The computer program product of claim 11, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256, or 512 bits.

15. The computer program product of claim 11, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide word.

16. A method for verifying an integrity of a coherent shared memory using inline coding, the coherent shared memory comprising a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the plurality of bus masters comprising corresponding cache memory, the method comprising:

an active stage step, wherein the active stage step comprises;

writing by each of the plurality of bus masters, a corresponding data to at least one memory unit from the plurality of memory units;

updating status corresponding to the at least one memory unit in a status database to modified state;

rewriting contents of the corresponding cache memory to the coherent shared memory; and

a verification stage step, wherein the verification stage step comprises;

reading back the corresponding data written by each of the plurality of bus masters, from the at least one memory unit;

comparing the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is a substantially similar to the corresponding data; and

updating and/or maintaining the status corresponding to the at least one memory unit in the status database to at least one of;

a verified state, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

the modified state, on the event of a mismatch between the data read back and the expected data written by at least one of the plurality of bus masters.

17. The method according to claim 16, wherein the plurality of bus masters is any one of a PPC440 PPC464, PPC476 and DMA.

18. The method according to claim 16, wherein the shared memory is any one of a DDR1, DDR2, DDR3 and SRAM memory.

19. The method according to claim 16, wherein the plurality of memory units is any one of 4, 8, 16, 32, 64, 128, 256 or 512 bits.

20. The method according to claim 16, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide.