PROCESSORS, METHODS, AND SYSTEMS TO RELAX SYNCHRONIZATION OF ACCESSES TO SHARED MEMORY
First Claim
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1. A processor comprising:
- a plurality of logical processors;
a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory; and
memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
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Abstract
A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
19 Citations
23 Claims
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1. A processor comprising:
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a plurality of logical processors; a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory; and memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method in a processor comprising:
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fetching a set of instructions for a first logical processor of a plurality of logical processors, the set of instructions including a memory access synchronization instruction to synchronize accesses to a memory; and accessing the memory from the first logical processor without respecting the synchronization of the memory access synchronization instruction. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A system to process instructions comprising:
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an interconnect; a processor coupled with the interconnect; and a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM to store instructions that, when executed by a machine, will cause the machine to perform operations comprising; determining to allow a first logical processor, of a plurality of logical processors of the processor, to operate in a relaxed memory access synchronization mode; and modifying one or more architecturally-visible bits of the processor to indicate that the first logical processor is allowed to operate in the relaxed memory access synchronization mode, wherein, when allowed to operate in the relaxed memory access synchronization mode, the first logical processor is to prevent a memory access synchronization instruction from synchronizing accesses to a memory. - View Dependent Claims (20, 21)
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22. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions that, if executed by a machine, will cause the machine to perform operations comprising:
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determining to allow a first logical processor, of a plurality of logical processors of the machine, to operate in a relaxed memory access synchronization mode; and modifying one or more architecturally-visible bits of the machine to indicate that the first logical processor is allowed to operate in the relaxed memory access synchronization mode, wherein, when allowed to operate in the relaxed memory access synchronization mode, the first logical processor is to prevent a memory access synchronization instruction from synchronizing accesses to a memory. - View Dependent Claims (23)
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Specification