MULTI-READ PORT MEMORY

• US 20140281284A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Block, Stefan G., Zhou, Ting, Grinchuk, Mikhail I., Bolotov, Anatoli A., Ivanovic, Lav D.
• Application Number:
  US13/833,691
• Publication Number:
  US 20140281284A1
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.

Claims

1. A memory operative to receive a multi-port read request and furnish data associated with a first port, a second port, and a third port in response to the multi-port read request, the memory comprising:

a first memory comprising a first memory module, a second memory module, and a third memory module configured as a first parity module;

a second memory comprising a fourth memory module, a fifth memory module, and a sixth memory module configured as a second parity module;

a third memory comprising a seventh memory module, an eighth memory module, and a ninth memory module configured as a third parity module; and

a controller operatively coupled with the first memory, the second memory, and the third memory and configured to receive a multi-port read request associated with first data stored at a first memory address associated with the first port, second data stored at a second memory address associated with the second port, and third data stored at a third memory address associated with the third port, wherein, when the first memory address, the second memory address, and the third memory address are associated with the first memory module, the controller is operatively configured to retrieve the first data from the first memory module, reconstruct the second data using data from the second memory module and the first parity module, reconstruct the third data using data from the fourth memory module and the seventh memory module, and provide the first data, the second data, and the third data in response to the multi-port read request.

2. The memory as recited in claim 1, wherein the multi-port read request is further associated with fourth data stored at a fourth memory address associated with a fourth port, and the controller is operatively configured to reconstruct the fourth data using data from the fifth memory module, the second parity module, the eighth memory module, and the third parity module when the first memory address, the second memory address, the third memory address, and the fourth memory address are associated with the first memory module.

3. The memory as recited in claim 1, wherein at least one of the first memory module, the second memory module, the third memory module, the fourth memory module, the fifth memory module, the sixth memory module, the seventh memory module, the eighth memory module, or the ninth memory module comprises a single-port memory module.

4. The memory as recited in claim 1, wherein the first memory further comprises a tenth memory module and an eleventh memory module, and the first parity module is associated with the first memory module, the second memory module, the tenth memory module, and the eleventh memory module.

5. The memory as recited in claim 1, wherein the first memory further comprises a tenth memory module, an eleventh memory module, a twelfth memory module configured as a fourth parity module, a thirteenth memory module configured as a fifth parity module, and a fourteenth memory module configured as a sixth parity module, the first parity module is associated with the first memory module and the second memory module, the fourth parity module is associated with the tenth memory module and the eleventh memory module, the fifth parity module is associated with the first memory module and the tenth memory module, and the sixth parity module is associated with the second memory module and the eleventh memory module.

6. The memory as recited in claim 1, wherein the first memory further comprises a tenth memory module, an eleventh memory module, a twelfth memory module configured as a fourth parity module, a thirteenth memory module configured as a fifth parity module, a fourteenth memory module configured as a sixth parity module, and a fifteenth memory module configured as a seventh parity module, the first parity module is associated with the first memory module and the second memory module, the fourth parity module is associated with the tenth memory module and the eleventh memory module, the fifth parity module is associated with the first memory module and the tenth memory module, the sixth parity module is associated with the second memory module and the eleventh memory module, and the seventh parity module is associated with the first memory module, the second memory module, the tenth memory module, and the eleventh memory module.

7. The memory as recited in claim 1, wherein the memory is included in an array of memories.

8. The memory as recited in claim 1, wherein the memory is fabricated in an integrated circuit.

9. A tangible computer-readable storage medium having computer executable instructions for receiving a multi-port read request and furnishing data associated with a first port, a second port, and a third port in response to the multi-port read request, the computer executable instructions comprising:

receiving a multi-port read request for retrieval of data stored in a first memory comprising a first memory module, a second memory module, and a third memory module configured as a first parity module;

a second memory comprising a fourth memory module, a fifth memory module, and a sixth memory module configured as a second parity module; and

a third memory comprising a seventh memory module, an eighth memory module, and a ninth memory module configured as a third parity module, the multi-port read request associated with first data stored at a first memory address associated with the first port, second data stored at a second memory address associated with the second port, and third data stored at a third memory address associated with the third port;

when the first memory address, the second memory address, and the third memory address are associated with the first memory module, retrieving the first data from the first memory module, reconstructing the second data using data from the second memory module and the first parity module, and reconstructing the third data using data from the fourth memory module and the seventh memory module; and

providing the first data, the second data, and the third data in response to the multi-port read request.

10. The tangible computer-readable storage medium as recited in claim 9, wherein the multi-port read request is further associated with fourth data stored at a fourth memory address associated with a fourth port, and the computer executable instructions further comprise:

when the first memory address, the second memory address, and the third memory address are associated with the first memory module, reconstructing the fourth data using data from the fifth memory module, the second parity module, the eighth memory module, and the third parity module; and

providing the fourth data in response to the multi-port read request.

11. The tangible computer-readable storage medium as recited in claim 9, wherein at least one of the first memory module, the second memory module, the third memory module, the fourth memory module, the fifth memory module, or the sixth memory module comprises a single-port memory module.

12. The tangible computer-readable storage medium as recited in claim 9, wherein the first memory further comprises a tenth memory module and an eleventh memory module, and the first parity module is associated with the first memory module, the second memory module, the tenth memory module, and the eleventh memory module.

13. The tangible computer-readable storage medium as recited in claim 9, wherein the first memory further comprises a tenth memory module, an eleventh memory module, a twelfth memory module configured as a fourth parity module, a thirteenth memory module configured as a fifth parity module, and a fourteenth memory module configured as a sixth parity module, the first parity module is associated with the first memory module and the second memory module, the fourth parity module is associated with the tenth memory module and the eleventh memory module, the fifth parity module is associated with the first memory module and the tenth memory module, and the sixth parity module is associated with the second memory module and the eleventh memory module.

14. The tangible computer-readable storage medium as recited in claim 9, wherein the first memory further comprises a tenth memory module, an eleventh memory module, a twelfth memory module configured as a fourth parity module, a thirteenth memory module configured as a fifth parity module, a fourteenth memory module configured as a sixth parity module, and a fifteenth memory module configured as a seventh parity module, the first parity module is associated with the first memory module and the second memory module, the fourth parity module is associated with the tenth memory module and the eleventh memory module, the fifth parity module is associated with the first memory module and the tenth memory module, the sixth parity module is associated with the second memory module and the eleventh memory module, and the seventh parity module is associated with the first memory module, the second memory module, the tenth memory module, and the eleventh memory module.

15. The tangible computer-readable storage medium as recited in claim 9, wherein the first memory, the second memory, and the third memory are included in a first memory array, and the first memory array is included in a memory comprising an array of first memory arrays.

16. A memory operative to receive a multi-port read request and furnish data associated with a first port, a second port, and a third port in response to the multi-port read request, the memory comprising:

a first memory comprising a first memory module, a second memory module, a third memory module configured as a first parity module, and a first parity register;

a second memory comprising a fourth memory module, a fifth memory module, a sixth memory module configured as a second parity module, and a second parity register;

a third memory comprising a seventh memory module, an eighth memory module, a ninth memory module configured as a third parity module, and a third parity register;

a fourth parity register; and

a controller operatively coupled with the first memory, the second memory, the third memory, and the fourth parity register, and configured to receive a multi-port read request associated with first data stored at a first memory address associated with the first port, second data stored at a second memory address associated with the second port, and third data stored at a third memory address associated with the third port, wherein, when the first memory address, the second memory address, and the third memory address are associated with the first memory module, the controller is operatively configured to retrieve the first data from the first memory module, reconstruct the second data using data from the second memory module and the first parity module, reconstruct the third data using data from the fourth memory module and the seventh memory module, and provide the first data, the second data, and the third data in response to the multi-port read request.

17. The memory as recited in claim 16, wherein the multi-port read request is further associated with fourth data stored at a fourth memory address associated with a fourth port, and the controller is operatively configured to reconstruct the fourth data using data from the fifth memory module, the second parity module, the eighth memory module, and the third parity module when the first memory address, the second memory address, the third memory address, and the fourth memory address are associated with the first memory module.

18. The memory as recited in claim 16, wherein at least one of the first memory module, the second memory module, the third memory module, the fourth memory module, the fifth memory module, the sixth memory module, the seventh memory module, the eighth memory module, or the ninth memory module comprises a single-port memory module.

19. The memory as recited in claim 16, wherein the first memory further comprises a tenth memory module and an eleventh memory module, and the first parity module is associated with the first memory module, the second memory module, the tenth memory module, and the eleventh memory module.

20. The memory as recited in claim 16, wherein the first memory further comprises a tenth memory module, an eleventh memory module, a twelfth memory module configured as a fourth parity module, a thirteenth memory module configured as a fifth parity module, and a fourteenth memory module configured as a sixth parity module, the first parity module is associated with the first memory module and the second memory module, the fourth parity module is associated with the tenth memory module and the eleventh memory module, the fifth parity module is associated with the first memory module and the tenth memory module, and the sixth parity module is associated with the second memory module and the eleventh memory module.