SYSTEMS AND METHODS FOR MEMORY SYSTEM MANAGEMENT BASED ON THERMAL INFORMATION OF A MEMORY SYSTEM

• US 20140281311A1
• Filed: 10/16/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Walker, Robert, Roberts, David A.
• Granted Patent: US 9,342,443 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Claims

1. A method, performed by a memory controller, of mapping a first logical memory address to an address in a memory system, the method comprising:

receiving a memory allocation request, the memory allocation request including the first logical memory address; and

mapping the first logical memory address to the address in a first memory region of the memory system based on thermal data for memory regions of the memory system.

2. The method of claim 1, further comprising:

storing the thermal data in a table, and wherein

the first memory region has a lowest temperature of the memory regions of the memory system.

3. The method of claim 2, further comprising:

storing a default value for thermal data for each of the memory regions, the default value being based on a characteristic of each of the memory regions.

4. The method of claim 3, further comprising:

updating thermal data in the table based on a sensed temperature during operation of the memory regions; and

remapping the first logical memory address to an address in a second memory region based on the updated thermal data.

5. The method of claim 4, wherein the remapping comprises copying data from the first memory region to the second memory region.

6. The method of claim 1, further comprising:

mapping a second logical memory address to a second memory region subsequent to mapping the first logical memory address, the second memory region having a higher temperature than the first memory region.

7. The method of claim 1, further comprising:

mapping physical data corresponding to the first logical memory address across two or more memory regions of the memory system;

accessing physical data in each of the two or more memory regions.

8. A method, performed by a host processor, for allocating memory in a memory system to a process executed on the host processor, the method comprising:

querying a table for temperatures of regions of the memory system;

creating an ordered list of regions of the memory system based on the temperatures; and

requesting allocation to a region based on a position of the region in the ordered list.

9. The method of claim 8, wherein the requesting is further based on a characteristic of the process.

10. The method of claim 8, further comprising:

receiving an indication that the temperatures of the regions have changed; and

reordering the ordered list based on the updated temperatures.

11. The method of claim 10, further comprising:

remapping a logical address corresponding to the allocation from a first memory region to a second memory region based on receiving updated temperature information, the remapping including copying data from the first memory region to the second memory region.

12. The method of claim 10, further comprising:

remapping the process from a first processing unit of the host processor to a second processing unit of the host processor based on receiving updated temperature information.

13. The method of claim 8, wherein the ordered list is further ordered based on a physical location of the regions of the memory system.

14. A computer-readable medium comprising instructions that, when executed on a machine, cause the machine to:

maintain a list of available regions of a memory system, the list in an order based on temperatures of the available regions;

request an allocation, to a process executing on the machine, of a first address in a first available region in the list based on the order of the first available region in the list and further based on a characteristic of the process.

15. The computer-readable medium of claim 14, further comprising instructions that, when executed on the machine, cause the machine to:

receiving updated temperature data;

reorder the list based on the updated temperature data;

allocate a second process to be mapped to a second address in a second available region based on the reordered list.

16. The computer-readable medium of claim 14, wherein the temperatures are default temperatures based on a predicted temperature of the corresponding available region, the predicted temperature being based on a physical characteristic of the corresponding available region.

17. A memory apparatus comprising:

a memory die including a plurality of regions of memory cells, two or more of the plurality of regions of memory cells each including a thermal sensor for sensing a temperature of a corresponding region of memory cells.

18. The apparatus of claim 17, further comprising:

thermal control logic (TCL) to

read the thermal sensors, and

provide temperature values based on the readings to a table of temperature values.

19. The apparatus of claim 18, wherein the TCL continuously reads the thermal sensors.

20. The apparatus of claim 18, wherein the TCL reads the thermal sensors periodically.

21. The apparatus of claim 18, wherein the TCL continuously reads the thermal sensors if a status of the memory system is a first status, and the TCL reads the thermal sensors periodically during if the status of the memory system is a second status different from the first status.

22. The apparatus of claim 18, wherein the TCL reads a plurality of thermal sensors, at least two of the plurality of thermal sensors corresponding to different regions of memory cells.

23. The apparatus of claim 22, wherein the TCL transmits thermal information to a host processor.

24. The apparatus of claim 22, wherein the TCL receives thermal information from a host processor.

25. The apparatus of claim 17, further comprising a logic chip coupled to the memory die.

26. The apparatus of claim 25, wherein the logic chip further includes a thermal sensor for measuring a temperature of the logic chip.

27. The apparatus of claim 26, wherein the apparatus comprises a plurality of memory dies arranged in a vertical stack.

28. The apparatus of claim 27, wherein

each of the plurality of memory dies includes a thermal sensor, each of the thermal sensors transmitting information

to each other of the plurality of memory dies, and

to thermal control logic.

29. A system comprising:

a memory system having a memory die, the memory die including a plurality of regions of memory cells and at least two of the plurality of regions including a thermal sensor;

a processor to request allocation of memory in the memory system;

a memory configured to store temperature data of the plurality of regions of memory cells; and

a memory controller to map a logical address to a physical address of the memory system based on an allocation request from the processor.

30. The system of claim 29, wherein the memory system further comprises a logic die and the memory system includes a plurality of memory dies arranged in a stack.

31. The system of claim 30, wherein the logic die further includes thermal control logic for adjusting a refresh rate of a region of the memory system based on a temperature of the region.

32. The system of claim 29, wherein the memory die further includes thermal control logic for adjusting a refresh rate of a region of the memory die based on a temperature of the region.

33. The system of claim 29, further comprising:

a translation lookaside buffer (TLB) to provide logical address translation between the processor and the memory controller.

34. A method for operating a memory system, the method comprising:

reading temperature values periodically, from thermal sensors, of a plurality of regions of the memory system;

setting a refresh rate for each of the plurality of regions of the memory system based on the temperatures.

35. The method of claim 34, further comprising:

adjusting time intervals between readings based on the temperature values.

36. The method of claim 35, further comprising:

reducing the time intervals between readings upon a reading of a large change in temperatures.

37. The method of claim 35, further comprising:

increasing the time intervals between readings if the temperatures remain unchanged over a number of readings.

38. The method of claim 35, further comprising:

transmitting readings from a first memory region to a second memory region and from the second memory region to the first memory region.

39. The method of claim 38, further comprising:

performing allocation and migration decisions based on the transmitted readings.

40. A memory controller for a memory system, the memory system including a memory die having regions of memory cells, the memory controller comprising:

a memory configured to store temperatures of the regions of memory cells; and

logic to map a logical memory address, received from a processor in an allocation request, to an address of a region based on the stored temperatures.

41. A method for throttling memory transactions, the method comprising:

receiving a request for a memory transaction accessing a location within a physical memory region;

retrieving a priority level of the request; and

reserving a bandwidth for the memory transaction based on the priority level of the request and based on a temperature of the physical memory region.

42. The method of claim 41, further comprising:

determining that the physical memory region is in a first temperature state;

inhibiting the request from accessing the location based on the determining; and

transmitting an error message to a host processor to notify of the inhibiting.

43. The method of claim 41, wherein bandwidth is reserved for the memory transaction based on an identity of a network including a processor from which the memory transaction is sent.

44. The method of claim 43, wherein the processor receives a network identifier based on a virtualization protocol.

45. The method of claim 44, wherein the virtualization protocol is an ARM Advanced Extensible Interface (AXI) bus virtualization protocol.

46. A method comprising any combination of operations herein to map data or relocate data in a memory system based on thermal information of the memory system.

47. A system comprising any combination of components discussed herein to map data or relocate data based on thermal information of memory regions of the system.