MULTI-THREADED MEMORY MANAGEMENT

• US 20140281363A1
• Filed: 08/23/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Tian, Chen, Waddington, Daniel G.
• Granted Patent: US 9,135,183 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.

Claims

1. A method for memory management comprising:

maintaining a first mapping structure for each thread of a multi-threaded process;

maintaining a second mapping structure for each core of a multi-core processing device;

maintaining a global mapping structure for shared memory mappings; and

during thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.

2. The method of claim 1, wherein the first mapping structure comprises a per-thread virtual-physical address mapping structure (VPMS), and the second mapping structure comprises a per-core local VPMS.

3. The method of claim 2, wherein translation lookaside buffer (TLB) flushing is avoided based on the copy during thread context switches.

4. The method of claim 3, wherein each page-mapping base address register comprises a VPMS base address register (BAR).

5. The method of claim 4, wherein each VPMS BAR points to an address of a corresponding per-core local VPMS.

6. The method of claim 4, further comprising:

partitioning virtual memory used by each thread of the multi-threaded process into an instruction region, a private memory region, and a shared memory region.

7. The method of claim 6, wherein each instruction region comprises a plurality of instructions for the multi-threaded process and is shared by each of the threads.

8. The method of claim 7, wherein each private memory region comprises a corresponding thread-local heap and stack data.

9. The method of claim 8, wherein the global mapping structure comprises a global VPMS that comprises mapping entries for each shared memory region.

10. The method of claim 9, wherein lock synchronization is required when accessing shared memory entries in both the global VPMS and a local VPMS.

11. The method of claim 10, further comprising:

synchronizing the local VPMS and the global VPMS based on a thread page-fault that occurs upon a particular thread attempting to access a particular shared memory region.

12. A system comprising:

a multi-core processor having a plurality of processor cores each coupled to a page-mapping base address register; and

a memory including a mapping architecture comprising;

a first mapping structure for each thread of a multi-threaded process executed by the plurality of cores;

a second mapping structure for each core of the plurality of cores; and

a global mapping structure for shared memory mappings of each thread of the multi-threaded process; and

a page-fault handler that synchronizes data in the global mapping structure and a particular second mapping structure.

13. The system of claim 12, wherein the first mapping structure comprises a per-thread virtual-physical address mapping structure (VPMS), and the second mapping structure comprises a per-core local VPMS.

14. The system of claim 13, wherein each core of the plurality of processor cores is coupled to a translation lookaside buffer (TLB), wherein TLB flushing is avoided based on performing a copy process performed during thread context switches without modifying the page-mapping base address register of each core of the plurality of processor cores.

15. The system of claim 14, wherein each page-mapping base address register comprises a VPMS base address register (BAR), and each VPMS BAR points to an address of a corresponding per-core local VPMS.

16. The system of claim 15, wherein virtual memory used by each thread of the multi-threaded process comprises an instruction region, a private memory region, and a shared memory region.

17. The system of claim 16, wherein each instruction region comprises a plurality of instructions for the multi-threaded process and is shared by each of the threads, and each private memory region comprises a corresponding thread-local heap and stack data.

18. The system of claim 17, wherein the global mapping structure comprises a global VPMS that comprises mapping entries for each shared memory region.

19. The system of claim 18, wherein lock synchronization is required when accessing shared memory entries in both the global VPMS and a local VPMS.

20. The system of claim 19, wherein the page-fault handler synchronizes the particular local VPMS and the global VPMS based on a thread page-fault that occurs upon a particular thread attempting to access a particular shared memory region.

21. A non-transitory computer-readable medium having instructions which when executed on a computer perform a method comprising:

creating a first mapping structure for each thread of a multi-threaded process;

creating a second mapping structure for each core of a multi-core processing device;

creating a global mapping structure for maintaining shared memory mappings; and

performing a copy of thread context entries during thread context switches without modifying a page-mapping base address register of each core of the multi-core processing device.

22. The medium of claim 21, wherein the first mapping structure comprises a per-thread virtual-physical address mapping structure (VPMS), and the second mapping structure comprises a per-core local VPMS.

23. The medium of claim 22, wherein each core of the multi-core processing device includes a translation lookaside buffer (TLB), and TLB flushing is avoided based on the copy during thread context switches.

24. The medium of claim 23, wherein each page-mapping base address register comprises a VPMS base address register (BAR), and each VPMS BAR points to an address of a corresponding per-core local VPMS.

25. The medium of claim 24, further comprising:

partitioning virtual memory used by each thread of the multi-threaded process into an instruction region, a private memory region, and a shared memory region, wherein each instruction region comprises a plurality of instructions for the multi-threaded process and is shared by each of the threads, and each private memory region comprises a corresponding thread-local heap and stack data.

26. The medium of claim 25, wherein the global mapping structure comprises a global VPMS that comprises mapping entries for each shared memory region, wherein lock synchronization is required when accessing shared memory entries in both the global VPMS and a particular local VPMS.

27. The medium of claim 26, further comprising:

synchronizing the particular local VPMS and the global VPMS based on a thread page-fault that occurs upon a particular thread attempting to access a particular shared memory region.

28. A server comprising:

a multi-core processor having a plurality of processor cores, wherein each processing core comprising a page-mapping base address register and a translation lookaside buffer (TLB);

a plurality of page directories, wherein each processing core of the plurality of processing cores is coupled to a corresponding page directory;

a plurality of page tables, wherein each processing core of the plurality of processing cores is coupled to a corresponding page table; and

a global page table coupled to each page directory of the plurality of page directories.

29. The server of claim 28, further comprising a thread scheduler for scheduling a plurality of threads for a multi-threaded process that is executed by the plurality of processing cores, wherein virtual memory used by each thread of the multi-threaded process comprises an instruction region, a private memory region, and a shared memory region.

30. The server of claim 29, wherein lock synchronization is required when accessing shared memory entries in both the global page table and a particular page directory, wherein a page-fault handler synchronizes the particular page directory and the global page table based on a thread page-fault that occurs upon a particular thread attempting to access a particular shared memory region.