METHOD AND APPARATUS FOR NEAREST POTENTIAL STORE TAGGING

• US 20140281409A1
• Filed: 03/13/2014
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Soft Machines Inc. (Intel Corporation)
• Inventors: SINGH, Mandeep, ABDALLAH, Mohammad A.
• Granted Patent: US 10,467,010 B2
• Time in Patent Office: Days
• US Class Current: 712/216
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags

Abstract

A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.

Claims

1. A method for performing memory disambiguation in an out-of-order microprocessor pipeline, said method comprising:

storing a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a RAW violation in conjunction with said load operation;

issuing said load operation from an instruction scheduling module;

acquiring data for said load operation speculatively after said load operation has arrived at a load store queue module;

determining if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag; and

gating a validation process for said load operation in response to said determining.

2. The method of claim 1, further comprising:

in response to a determination that said identification number associated with said last contiguous issued store is equal to or greater than said tag, validating said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any of said stores has potential to result in a RAW hazard, wherein said stores are older than said load operation.

3. The method of claim 2, further comprising:

committing said load operation in response to a determination that none of said stores has potential to result in a RAW hazard.

4. The method of claim 1, further comprising broadcasting by said instruction scheduling module said identification number associated with said last contiguous issued store during every cycle of said out-of-order microprocessor pipeline.

5. The method of claim 4, wherein said determining is performed in response to said instruction scheduling module broadcasting said identification number associated with said last contiguous issued store.

6. The method of claim 1, wherein said identification number associated with said tag is assigned by a reorder buffer (ROB).

7. The method of claim 1, wherein said storing is performed using an inheritance process, wherein said identification number associated with said tag is inherited from an instruction prior to said load operation.

8. A processor unit configured to perform a method for performing memory disambiguation in an out-of-order microprocessor pipeline, said method comprising:

storing a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a RAW violation in conjunction with said load operation;

issuing said load operation from an instruction scheduling module;

acquiring data for said load operation speculatively after said load operation has arrived at a load store queue module;

determining if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag; and

gating a validation process for said load operation in response to said determining.

9. The processor unit as described in claim 8, wherein said method further comprises:

in response to a determination that said identification number associated with said last contiguous issued store is equal to or greater than said tag, validating said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any of said stores has potential to result in a RAW hazard, wherein said stores are older than said load operation.

10. The processor unit as described in claim 9, wherein said method further comprises:

committing said load operation in response to a determination that none of said stores has potential to result in a RAW hazard.

11. The processor unit as described in claim 8, wherein said instruction scheduling module is operable to broadcast said identification number associated with said last contiguous issued store during every cycle of said out-of-order microprocessor pipeline.

12. The processor unit as described in claim 11, wherein said determining is performed in response to said instruction scheduling module broadcasting said identification number associated with said last contiguous issued store.

13. The processor unit as described in claim 8, wherein said identification number associated with said tag is assigned by a reorder buffer (ROB).

14. The processor unit as described in claim 8, wherein said storing is performed using an inheritance process, wherein said identification number associated with said tag is inherited from an instruction prior to said load operation.

15. An apparatus configured to perform a method for performing memory disambiguation in an out-of-order microprocessor pipeline, said apparatus comprising:

a memory;

a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to;

store a tag with a load operation, wherein said tag is an identification number representing a store instruction nearest to said load operation, wherein said store instruction is older with respect to said load operation and wherein said store has potential to result in a RAW violation in conjunction with said load operation;

issue said load operation from an instruction scheduling module;

acquire data for said load operation speculatively after said load operation has arrived at a load store queue module;

determine if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag; and

gate a validation process for said load operation in response to a determination of whether said identification number associated with said last contiguous issued store is equal to or greater than said tag.

16. The apparatus of claim 15, wherein in response to a determination that said identification number associated with said last contiguous issued store is equal to or greater than said tag, said processor is further configured to:

validate said data acquired by said load operation by performing an address check against stores in said load store queue module to determine if any of said stores has potential to result in a RAW hazard, wherein said stores are older than said load operation.

17. The apparatus of claim 16, wherein said processor is further configured to:

commit said load operation in response to a determination that none of said stores has potential to result in a RAW hazard.

18. The apparatus of claim 15, wherein said instruction scheduling module is operable to broadcast said identification number associated with said last contiguous issued store during every cycle of said out-of-order microprocessor pipeline.

19. The apparatus of claim 18, wherein said processor is further configured to determine if an identification number associated with a last contiguous issued store with respect to said load operation is equal to or greater than said tag in response to said instruction scheduling module broadcasting said identification number associated with said last contiguous issued store.

20. The apparatus of claim 15, wherein said identification number associated with said tag is assigned by a reorder buffer (ROB).