PHY Based Wake Up From Low Power Mode Operation

• US 20140281626A1
• Filed: 03/15/2013
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Younger, Scott Thomas, Priborsky, Anthony L., Skaar, Thomas John, Behnke, Eric James
• Granted Patent: US 9,411,394 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line.

Claims

1. An apparatus comprising:

a system on chip (SOC) integrated circuit comprising a first region having a processing core and a second region electrically isolated from the first region and comprising an always on domain power island with a power control block, the power control block comprising an energy detector coupled to a host input line;

a first power supply module adapted to selectively apply power to the first region responsive to a main switch; and

a second power supply module adapted to continuously supply power to the second region, wherein the power control block opens the main switch to enter a low power mode during which no electrical power is supplied to the first region, and the power control block closes the main switch to resume application of electrical power to the first region responsive to a detection of electrical energy on the host input line by the energy detector.

2. The apparatus of claim 1, in which the power control block further comprises a qualification logic block which detects a host wake up signal from the host device on the host input line from a sequence of outputs from the energy detector.

3. The apparatus of claim 2, in which the power control block further comprises a low power clock circuit that outputs a single phase internal clock signal to the qualification logic block so that no external clock signal is supplied to the AOD.

4. The apparatus of claim 1, in which the energy detector detects a host wake up signal on the host input line as a differential signal on a pair of host phy connection pins.

5. The apparatus of claim 2, in which the power control block further comprises a switch control circuit which transitions the main switch to the closed state responsive to the qualification logic block.

6. The apparatus of claim 1, in which the power control block further comprises a processing core interface circuit which transfers status information to the processing core of the first portion that identifies a selected one of a plurality of events that induced the power control block to close the main switch and resume application of power to the first region.

7. The apparatus of claim 6, in which the plurality of events include a timeout signal from a timer initiated at a commencement of the low power mode period, a detected voltage fault during the low power mode period, and a detected wake up signal from the host input line.

8. The apparatus of claim 1, in which the first and second power supply modules respectively generate the first and second supply voltages responsive to an input host supply voltage from the input host supply terminal, and wherein the input host supply voltage is not supplied to the first power supply module responsive to the main switch being transitioned to said open state.

9. The apparatus of claim 1, in which the power control block transitions the main switch to an open state by transmitting a power disable signal to the second power supply module responsive to a control signal transmitted to the power control block from the processing core.

10. The apparatus of claim 1, in which the second region of the SOC further comprises a voltage sense circuit which monitors the second supply voltage during the low power mode and transmits a voltage fault signal to the power control block responsive to a magnitude of the second supply voltage during the low power mode and a predetermined threshold.

11. The apparatus of claim 1, in which the first region of the SOC further comprises a secondary detector adapted to detect a wake up signal from the host input line.

12. The apparatus of claim 1, in which the processing core, the power control block and the voltage sense circuit are each formed of a respective plurality of transistors incorporated into the SOC.

13. The apparatus of claim 1, in which the power control block subsequently transitions the main switch to a closed position to resume application of the first supply voltage to the first region at a conclusion of the low power mode, in which the power control block transmits a status indication to the processing core indicative of a presence or an absence of a fault condition detected during the low power mode, and in which the processing core initiates a cold boot reinitialization or a warm boot reinitialization responsive to the status indication from the power control block.

14. The apparatus of claim 1, in which the SOC is characterized as a storage controller of a data storage device, and the apparatus further comprises a memory adapted to store data from a host device responsive to control inputs provided by the storage controller.

20. The method of claim 14, in which the SOC is characterized as a storage controller of a data storage device.

15. A method comprising:

connecting a system on chip (SOC) integrated circuit to a power interface, the SOC comprising a first region having a processing core and a second region electrically isolated from the first region as an always on domain power island having a power control block comprising an energy detector coupled to a host input line, the power interface comprising a first power supply module adapted to selectively apply first power to the first region and a second power supply module adapted to continuously supply second power to the second region, the second power supply module comprising a main switch between the first power supply module and a host input voltage terminal;

opening the main switch to place the SOC into a low power mode by removing electrical power from the first region; and

closing the main switch to return electrical power to the first region responsive to a detection of electrical energy on the host input line by the energy detector.

16. The method of claim 15, in which the power control block further comprises a qualification logic block, and the closing step further comprises detecting a host wake up signal from the host device on the host input line from a sequence of outputs from the energy detector.

17. The method of claim 16, in which the power control block further comprises a low power clock circuit, and the closing step further comprises outputting a single phase clock signal to the qualification logic block from the low power clock circuit during said detecting of the host wake up signal.

18. The method of claim 15, further comprising communicating status information from the power control block to the processing core indicative of an event that initiated the closing of the main switch.

19. The method of claim 18, in which the event comprises a selected one of a timeout signal from a timer initiated at a commencement of the low power mode period, a detected voltage fault during the low power mode period, or a detected wake up signal from the host input line.