ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF

• US 20140281716A1
• Filed: 03/13/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Azad, Sarosh I.
• Granted Patent: US 9,411,701 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Claims

1. An apparatus, comprising:

a system-on-chip having at least one analog block, an input/output interface, a data test block, and a processing unit;

wherein the processing unit is coupled to the input/output interface to control access to the at least one analog block;

wherein the data test block is coupled to the at least one analog block through the input/output interface;

wherein the processing unit is coupled to the data test block and configured to execute test code having at least one test pattern; and

wherein the data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

2. The apparatus according to claim 1, wherein the data test block comprises input control registers, output capture registers, a test pattern generator, and a test pattern checker.

3. The apparatus according to claim 2, wherein the test pattern generator comprises a linear feedback shift register and pseudo-random bit sequence generator.

4. The apparatus according to claim 2, wherein the test pattern checker comprises a linear feedback shift register and pseudo-random bit sequence checker.

5. The apparatus according to claim 2, wherein the input control registers and the output capture registers are accessible via the processing unit under control of the test code.

6. The apparatus according to claim 5, wherein:

the input control registers are to control test pattern generation by the test pattern generator responsive to the test pattern;

the output capture registers are to capture data sequences and data errors determined by the test pattern checker responsive to the test pattern; and

the test pattern is provided under control of the test pattern generator to the at least one analog block for loopback to the test pattern checker;

wherein the at least one analog block is at least one serializer-deserializer.

7. The apparatus according to claim 5, further comprising a link test block coupled to the at least one analog block through the input/output interface.

8. The apparatus according to claim 6, wherein the link test block comprises a configuration controller, a status monitor, a bit error rate tester, an eye scan controller, and a test interface.

9. The apparatus according to claim 8, wherein:

the link test block is separately controllable via the test interface to adjust operating parameters of the at least one analog block during operation thereof; and

the at least one analog block is at least one serializer-deserializer.

10. The apparatus according to claim 9, wherein the operating parameters comprise at least one analog parameter.

11. The apparatus according to claim 10, wherein:

the at least one serializer-deserializer includes control registers and finite state machines;

the configuration controller is configured to control the control registers to adjust at least one of the operating parameters during operation of the at least one serializer-deserializer; and

the status monitor is coupled to monitor status of the at least one serializer-deserializer and to capture each error output from the at least one serializer-deserializer on clock cycle granularity.

12. The apparatus according to claim 8, wherein:

the bit error rate tester is configured to determine a bit error rate using the test pattern; and

the test interface is coupled to provide the test pattern to the bit error rate tester.

13. The apparatus according to claim 8, wherein:

the processing unit is coupled to execute an application involving application data provided to the at least one analog block via an access controller coupled to the input/output interface and the processing unit;

the eye scan controller is configured to determine a data eye for the application data during execution of the application; and

the at least one analog block is at least one serializer-deserializer.

14. A method, comprising:

testing an analog block to loop back a data sequence;

providing configuration information to a configuration controller of a link test block;

configuring an analog block under control of the configuration controller responsive to the configuration information;

receiving the data sequence by a bit error rate tester of the link test block from the analog block;

wherein the bit error rate tester is configured with test pattern information;

wherein the data sequence is responsive to a test pattern associated with the test pattern information;

determining a bit error rate by the bit error rate tester for the data sequence; and

outputting the bit error rate.

15. The method according to claim 14, wherein the analog block is a serializer-deserializer, and wherein the testing comprises:

executing test code by a processing unit;

wherein the test code includes the test pattern information;

wherein the test code is configured to toggle inputs and outputs of the serializer-deserializer by,

loading a peripheral bus block of a test data block with the test pattern information for generation of the test pattern;

wherein the loading is controlled by the test code executed by the processing unit;

generating the data sequence responsive to the test pattern by a test pattern generator of the data test block;

sending the data sequence to the serializer-deserializer to toggle the inputs of the serializer-deserializer;

looping back the data sequence sent to toggle the outputs of the serializer-deserializer;

receiving the data sequence looped back by a test pattern checker of the data test block;

checking the data sequence received by the test pattern checker to generate test data for the serializer-deserializer;

capturing the test data from the test pattern checker responsive to the checking; and

outputting the test data to the processing unit.

16. The method according to claim 15, wherein the testing further comprises;

issuing a read for a state of operation of the serializer-deserializer from the test code;

providing a microcontroller bus transaction from the processing unit responsive to execution of the read of the test code; and

translating the microcontroller bus transaction to a peripheral bus transaction;

wherein the loading comprises registering the peripheral bus transaction by the peripheral bus block of the data test block to load the peripheral bus block with the test pattern information.

17. The method according to claim 16, further comprising:

receiving status information from the serializer-deserializer by a status monitor of the link test block;

wherein the status information is from a state machine of the serializer-deserializer;

wherein the status information is independently bused from the serializer-deserializer with respect to the data sequence looped back; and

outputting the status information.

18. The method according to claim 17, wherein the link test block comprises a test interface for the providing of the configuration information, the output of the status information, and the outputting of the bit error rate independently with respect to execution of the test code by the processing unit.

19. A method comprising:

providing configuration information to a configuration controller of a link test block;

configuring an analog block under control of the configuration controller responsive to the configuration information;

receiving application data by an eye scan controller of the link test block from the analog block via a first input/output bus;

generating a data eye by the eye scan controller responsive to the application data;

wherein the data eye is for settings of the analog block responsive to the configuration information; and

outputting the data eye.

20. The method according to claim 19, further comprising:

executing application code by a processing unit to generate the application data;

providing the application data from the processing unit to a media access controller; and

sending the application data from the media access controller to the analog block via a second input/output bus independent from the first input output bus;

wherein the application data is generated in parallel with outputting of the data eye.