SYSTEM AND METHOD FOR RANDOM NOISE GENERATION

• US 20140281762A1
• Filed: 01/30/2014
• Published: 09/18/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Norrie, Christopher I. W.
• Granted Patent: US 9,235,488 B2
• Time in Patent Office: Days
• US Class Current: 714/703
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/3927 Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs

Abstract

A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.

Claims

1. A method of generating a noisy log likelihood ratio (LLR) for testing an error correction circuit of a nonvolatile memory storage module, the method comprising:

generating a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module;

generating a random sample;

comparing the random sample to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs, each of the plurality of regions of the probability distribution curve having an associated noisy log likelihood ratio (LLR); and

replacing the random sample with the noisy LLR of the identified region to generate a noisy LLR for testing an error correction circuit of the nonvolatile memory storage module.

2. The method of claim 1, wherein generating a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module, further comprises:

identifying a probability distribution curve for the nonvolatile memory storage module;

dividing the probability distribution curve into a plurality of regions;

calculating the area under the probability distribution curve for each of the plurality of regions;

dividing a linear space proportionately according to the area under the probability distribution curve for each of the plurality of regions to generate a plurality of coefficients, the plurality of coefficients defining the plurality of regions.

3. The method of claim 1, wherein generating a random sample further comprises reading a sample from the nonvolatile memory storage module.

4. The method of claim 1, wherein generating a random sample further comprises generating a linear random number.

5. The method of claim 1, wherein the probability distribution curve is an additive white Gaussian noise (AWGN) probability distribution curve.

6. The method of claim 1, wherein the error correction circuit is a low-density parity-check (LDPC) error correction circuit.

7. The method of claim 1, wherein comparing the random sample to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs further comprises, performing a linear search of the plurality of coefficients.

8. The method of claim 1, wherein comparing the random sample to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs further comprises, performing a binary search of the plurality of coefficients.

9. A random noise generation module for generating a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module, the random noise generation module comprising:

a coefficient generator configured to generate a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module;

a comparator configured to compare a random sample received at the random noise generation module to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs, each of the plurality of regions of the probability distribution curve having an associated noisy log likelihood ratio (LLR); and

a noisy LLR replacement module configured to replace the random sample with the noisy LLR of the identified region to generate a noisy LLR for testing an error correction circuit of the nonvolatile memory storage module.

10. The random noise generation module of claim 9, wherein the coefficient generator is further configured to identify a probability distribution curve for the nonvolatile memory storage module, to divide the probability distribution curve into a plurality of regions, to calculate the area under the probability distribution curve for each of the plurality of regions and to divide a linear space proportionately according to the area under the probability distribution curve for each of the plurality of regions to generate a plurality of coefficients, the plurality of coefficients defining the plurality of regions.

11. The random noise generation module of claim 9, wherein the random sample is a sample read from the nonvolatile memory storage module.

12. The random noise generation module of claim 9, further comprising a linear random number generator and wherein the random sample is a linear random number generated by the linear random number generator.

13. The random noise generation module of claim 9, wherein the probability distribution curve is an additive white Gaussian noise (AWGN) probability distribution curve.

14. The random noise generation module of claim 9, wherein the nonvolatile memory storage module is a NAND-based flash memory module.

15. The random noise generation module of claim 9, wherein the error correction circuit is a low-density parity-check (LDPC) error correction circuit.

16. The random noise generation module of claim 9, wherein comparing the random sample to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs further comprises, performing a binary search of the plurality of coefficients.

17. The random noise generation module of claim 9, wherein comparing the random sample to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs further comprises, performing a linear search of the plurality of coefficients.

18. A system for testing an error correction circuit of a nonvolatile memory storage module, the system comprising:

a random noise generation module for generating a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module, the random noise generation module comprising;

a coefficient generator configured to identify a probability distribution curve for the nonvolatile memory storage module, to divide the probability distribution curve into a plurality of regions, to calculate the area under the probability distribution curve for each of the plurality of regions and to divide a linear space proportionately according to the area under the probability distribution curve for each of the plurality of regions to generate a plurality of coefficients, each of the plurality of regions of the probability distribution curve having an associated noisy log likelihood ratio (LLR);

a comparator configured to compare a random sample received at the system to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the random sample belongs;

a noisy LLR replacement module configured to replace the random sample with a noisy LLR of the identified region to generate a noisy LLR; and

a decoder configured to receive the noisy LLR from the nonvolatile memory controller and configured to decode an encoded codeword stored in the nonvolatile memory storage module to test the error correction code circuit of the nonvolatile memory storage module.

19. The system of claim 18, wherein the random noise generation module and the decoder are fabricated on the same integrated circuit die.

20. A method for testing an error correction circuit of a nonvolatile memory controller, the method comprising:

generating a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module;

generating an encoded codeword comprising a plurality of bits;

comparing the bits of the encoded codeword to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which each of the bits of the encoded codeword belongs, each of the plurality of regions of the probability distribution curve having an associated noisy log likelihood ratio (LLR);

replacing each bit of the encoded codeword with the noisy LLR of the identified region to generate a noisy encoded codeword; and

providing the noisy encoded codeword to a decoder coupled to the random noise generation module, the decoder configured to recover the codeword from the noisy encoded codeword to test the error correction code circuit of the nonvolatile memory storage module.