METHOD AND APPARATUS TO SCHEDULE STORE INSTRUCTIONS ACROSS ATOMIC REGIONS IN BINARY TRANSLATION
First Claim
1. An apparatus comprising:
- logic to perform binary translation of a code having a source binary program order, wherein one or more store instructions of the binary translated code are to be issued in a different order from the source binary program order of the one or more store instructions of the code, and wherein the one or more store instructions of the binary translated code are to be retired in the source binary program order.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.
20 Citations
27 Claims
-
1. An apparatus comprising:
logic to perform binary translation of a code having a source binary program order, wherein one or more store instructions of the binary translated code are to be issued in a different order from the source binary program order of the one or more store instructions of the code, and wherein the one or more store instructions of the binary translated code are to be retired in the source binary program order. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
10. A system comprising:
-
a memory; and a processor having logic to perform binary translation of a code having a source binary program order, wherein one or more store instructions of the binary translated code are to be issued in a different order from the source binary program order of the one or more store instructions of the code, and wherein the one or more store instructions of the binary translated code are to be retired in the source binary program order. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A method comprising:
performing binary translation of a code having a source binary program order, wherein one or more store instructions of the binary translated code are to be issued in a different order from the source binary program order of the one or more store instructions of the code, and wherein the one or more store instructions of the binary translated code are to be retired in the source binary program order. - View Dependent Claims (20, 21, 22, 24, 25, 26, 27)
-
23. The method of 22, wherein the method further comprises executing the binary translated code by performing the following steps:
-
subtracting the store offset indictor of each store instruction by the count if the store offset indicator is bigger than the count in response to the executed commit instruction; and subtracting the load offset indictor of each load instruction by the count if the load offset indicator is bigger than the count in response to the executed commit instruction.
-
Specification