NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20140284675A1
• Filed: 08/28/2013
• Published: 09/25/2014
• Est. Priority Date: 03/19/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: WATANABE, Nobutaka
• Granted Patent: US 8,890,229 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; and a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body. The stacked body includes a plurality of staircase regions. The each of the plurality of electrode layers includes an exposed portion. The exposed portion is not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers. And the exposed portion of each of the plurality of electrode layers is disposed in one of the plurality of staircase regions.

Claims

1. A nonvolatile semiconductor memory device comprising:

a foundation layer; and

a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body;

a select gate electrode provided on the stacked body;

a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body;

a first insulating film provided between the semiconductor layer and each of the plurality of electrode layers; and

a second insulating film provided between the select gate electrode and the semiconductor layer,

the stacked body including a plurality of staircase regions,

the each of the plurality of electrode layers including an exposed portion, and the exposed portion being not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers, and

the exposed portion of each of the plurality of electrode layers being disposed in one of the plurality of staircase regions.

2. The device according to claim 1, wherein each of the plurality of staircase regions includes first steps and second steps, the first steps are formed by at least one row of the exposed portions arranged in a first direction perpendicular to stacking direction of the stacked body, and the second steps are formed by at least one row of the exposed portions arranged in a second direction perpendicular to the stacking direction and the first direction.

3. The device according to claim 1, wherein the plurality of staircase regions are arranged in a row in longitudinal direction of the stacked body.

4. The device according to claim 1, wherein

the plurality of staircase regions include a first staircase region and a second staircase region,

the first staircase region and the second staircase region are arranged in the first direction,

the second staircase region is disposed on a side of the semiconductor layer than the first staircase region side, and

the exposed portion of each of the plurality of electrode layers in lower part of the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers in upper part of the stacked body is provided in the second staircase region, or

the exposed portion of each of the plurality of electrode layers in upper part of the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers in lower part of the stacked body is provided in the second staircase region.

5. The device according to claim 2, wherein a height difference between the exposed portion of any of the plurality of electrode layers and an exposed portion next the any of the plurality of electrode layers is thickness of a pair of the electrode layer and the insulating layer.

6. The device according to claim 2, wherein a height difference between the exposed portion of any of the plurality of electrode layers and an exposed portion next the any of the plurality of electrode layers is thickness of a plurality of pairs of the electrode layer and the insulating layer.

7. The device according to claim 1, wherein

the plurality of staircase regions include a first staircase region and a second staircase region,

the first staircase region and the second staircase region are arranged in the first direction,

the second staircase region is disposed on a side of the semiconductor layer than the first staircase region side, and

the exposed portion of each of the plurality of electrode layers at odd-numbered levels in the plurality of electrode layers stacked in the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers at even-numbered levels in the plurality of electrode layers is provided in the second staircase region, or

the exposed portion of each of the plurality of electrode layers at even-numbered levels in the plurality of electrode layers stacked in the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers at odd-numbered levels in the plurality of electrode layers is provided in the second staircase region.

8. The device according to claim 7, wherein a height difference between the exposed portion of any of the plurality of electrode layers and an exposed portion next the any of the plurality of electrode layers is thickness of a plurality of pairs of the electrode layer and the insulating layer.

9. The device according to claim 1, wherein the exposed portion has a rectangular planar shape.

10. The device according to claim 1, further comprising:

an interconnect connected to the exposed portion.

11. The device according to claim 4, wherein

the exposed portion of each of the plurality of electrode layers in lower half of the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers in upper half of the stacked body is provided in the second staircase region, or

the exposed portion of each of the plurality of electrode layers in upper half of the stacked body is provided in the first staircase region, and the exposed portion of each of the plurality of electrode layers in lower half of the stacked body is provided in the second staircase region.