VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN

• US 20140284695A1
• Filed: 01/09/2014
• Published: 09/25/2014
• Est. Priority Date: 03/19/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dong-Seog Eun, Joon-Hee Lee, Seung-Woo Paek
• Inventors: LEE, Joon-Hee, PAEK, Seung-Woo, WON, Jin-Yeon, EUN, Dong-Seog
• Granted Patent: US 9,281,414 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole, each of the gate electrodes including a portion in which a vertical width thereof is reduced with the approach to one end thereof; and

a vertical structure in the through-hole, the vertical structure including a gap-fill pattern in a middle of the through-hole, a channel pattern surrounding an outer surface of the gap-fill pattern, and a gate dielectric layer surrounding an outer surface of the channel pattern, and

the gate dielectric layer includes a tunneling layer in contact with the channel pattern, a charge trap layer in contact with the tunneling layer, a barrier layer in contact with the charge trap layer, and protective patterns,

each one of the protective patterns being between the barrier layer and one of the gate electrodes, and

each one of the protective patterns extending between two of the interlayer insulating layers and the protective patterns surround the portions of the gate electrodes in which the vertical width thereof is reduced.

2. The semiconductor device of claim 1, wherein the protective patterns include an oxide of silicon.

3. The semiconductor device of claim 1, wherein

each one of the gate electrodes includes an upper surface opposite a lower surface, a first lateral surface opposite a second lateral surface, and an upper inclined surface opposite a lower inclined surface,

the first lateral surface connects one end of the upper surface to one end of the lower surface,

the upper inclined surface connecting one end of the second lateral surface and an other end of the upper surface,

the lower inclined surface connecting an other end of the second lateral surface and an other end of the lower surface, and

a length of the second lateral surface is shorter than a length of the first lateral surface.

4. The semiconductor device of claim 3, wherein each one of the protective patterns includes:

an upper part between a lower surface of one of the interlayer insulating layers above and the upper inclined surface of an adjacent one of the gate electrodes;

a lower part between the lower surface of one of the interlayer insulating layers below and the lower inclined surface of the adjacent one of the gate electrodes, and

a body part connecting the upper part to the lower part.

5. The semiconductor device of claim 4, wherein

the upper part of each one of the protective patterns includes an inclined inner surface in contact with the upper inclined surface of one of the gate electrodes, and the lower part of each one of the protective patterns includes an inclined inner surface in contact with the lower inclined surface of one of the gate electrodes.

6. The semiconductor device of claim 5, further comprising:

blocking layers, each of one of the blocking layers having one surface in contact with the upper surface, lower surface, upper inclined surface, lower inclined surface, and second lateral surface of one of the gate electrodes, and each one of the blocking layer having an other surface in contact with parts of two interlayer insulating layers, the inclined upper and lower inner surfaces and one surface of the body part of one of the protective patterns.

7. The semiconductor device of claim 4, wherein the body part of each one of the protective patterns includes a protrusion that protrudes into the through-hole.

8. The semiconductor device of claim 6, wherein the barrier layer contacts exposed lateral surfaces of the interlayer insulating layers and the protrusions of the body parts of the protective patterns.

9. The semiconductor device of claim 1, wherein the channel pattern contacts a surface of the substrate that defines a bottom surface of the through-hole.

10. The semiconductor device of claim 1, further comprising:

a contact electrode on the gap-fill pattern and contacting the channel pattern.

11. The semiconductor device of claim 10, further comprising:

capping layers on the stacked structure, wherein the capping layers define a hole exposing an upper surface of the contact electrode.

12. The semiconductor device of claim 11, further comprising:

a conductive interconnection on the capping layers, wherein the conductive interconnection is electrically connected to the exposed contact electrode.

13. A semiconductor device, comprising:

a substrate;

a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole, each of the gate electrodes including a portion in which a vertical width thereof is reduced with the approach to one end thereof; and

a vertical structure in the through-hole, the vertical structure including a gap-fill pattern in a middle of the through-hole, a channel pattern surrounding an outer surface of the gap-fill pattern, and a gate dielectric layer surrounding an outer surface of the channel pattern, and

the gate dielectric layer includes a tunneling layer in contact with the channel pattern, a charge trap layer in contact with the tunneling layer, a protective layer in contact with the charge trap layer, and protective patterns that are integral with the protective layer,

the protective patterns extending to the gate electrodes, and surround the portions of the gate electrodes in which the vertical width is reduced.

14. The semiconductor device of claim 13, wherein the protective patterns include an oxide of silicon.

15. The semiconductor device of claim 13, further comprising:

a barrier layer between the charge trap layer and the protective patterns.

16. A semiconductor device, comprising:

a substrate;

a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole over the substrate, the gate electrodes each including a first portion between the through-hole and a second portion of the gate electrodes;

a channel pattern extending vertically in the through-hole over the substrate;

a tunneling layer surrounding the channel pattern;

a charge trap layer surrounding the tunneling layer; and

protective patterns surrounding the first portions of the gate electrodes, the protective patterns between the first portions of the gate electrodes and the charge trap layer.

17. The semiconductor device of claim 16, wherein

the first portions of the gate electrodes each have a thickness that gradually reduces from the second portions of the gate electrodes towards the through-hole, and

the protective patterns do not surround the second portions of the gate electrodes.

18. The semiconductor device of claim 16, further comprising:

a barrier layer between the protective patterns and the charge trap layer.

19. The semiconductor device of claim 16, further comprising:

a protective layer that extends vertically in the through-hole between the charge trap layer and the protective patterns, wherein

each one of the protective patterns extends from a side of the protective layer to surround the first portion of one of the gate electrodes.

20. The semiconductor device of claim 16, wherein

the protective patterns include an oxide of silicon,

the interlayer insulating layers include an oxide, and

the oxide of silicon in the protective patterns is more compact than the oxide of the interlayer insulating layers.