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VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN

  • US 20140284695A1
  • Filed: 01/09/2014
  • Published: 09/25/2014
  • Est. Priority Date: 03/19/2013
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a substrate;

    a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, the stacked structure defining a through-hole, each of the gate electrodes including a portion in which a vertical width thereof is reduced with the approach to one end thereof; and

    a vertical structure in the through-hole, the vertical structure including a gap-fill pattern in a middle of the through-hole, a channel pattern surrounding an outer surface of the gap-fill pattern, and a gate dielectric layer surrounding an outer surface of the channel pattern, andthe gate dielectric layer includes a tunneling layer in contact with the channel pattern, a charge trap layer in contact with the tunneling layer, a barrier layer in contact with the charge trap layer, and protective patterns,each one of the protective patterns being between the barrier layer and one of the gate electrodes, andeach one of the protective patterns extending between two of the interlayer insulating layers and the protective patterns surround the portions of the gate electrodes in which the vertical width thereof is reduced.

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