SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20140284790A1
• Filed: 03/13/2014
• Published: 09/25/2014
• Est. Priority Date: 03/21/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsumoto, Masahiro, Fujisawa, Masahiko, Maekawa, Kazuyoshi
• Granted Patent: US 9,406,628 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: C22C 21/12 with copper as the next major constituent
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05582 Two-layer coating
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/29339 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48664 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48864 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/85045 : using a corona discharge, e.g. electronic flame off [EFO]
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/20305 : Ultrasonic frequency [f] 100 Khz=<f< 125 KHz
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

Claims

1. A semiconductor device comprising:

a first insulating film formed on a principal surface of a semiconductor substrate;

an electrode pad formed on the first insulating film and formed of an alloy film to which Cu is added;

a second insulating film formed on the principal surface of the semiconductor substrate so as to cover the electrode pad;

a first opening formed in the second insulating film so as to expose a part of an upper surface of the electrode pad;

a plating film electrically connected to the electrode pad via the first opening; and

a plating adhesion film formed on an upper surface of the plating film,

wherein a concentration of the Cu added to the alloy film forming the electrode pad is 2 wt % or more.

2. The semiconductor device according to claim 1,

wherein the concentration of the Cu added to the alloy film forming the electrode pad is 2 wt % to 10 wt %.

3. The semiconductor device according to claim 1,

wherein a thickness of the alloy film forming the electrode pad is 0.3 μ

m to 3.0 μ

m.

4. The semiconductor device according to claim 1,

wherein the alloy film forming the electrode pad is an Al—

Cu alloy film.

5. The semiconductor device according to claim 1,

wherein the plating film is formed of a Ni film, a Ti film, a Cr film, or a stacked film formed by stacking any of them, and the plating adhesion film is formed of a Pd film, a Au film, or a stacked film formed by stacking the Pd film and the Au film.

6. The semiconductor device according to claim 1,

wherein a plating electrode film is formed between the electrode pad and the plating film.

7. The semiconductor device according to claim 6,

wherein the plating electrode film is formed of a Ti film, a Pd film, a Cr film, a Cu film, or a stacked film formed by stacking any of them.

8. The semiconductor device according to claim 1,

wherein Knoop hardness of the alloy film forming the electrode pad is 3 kg/mm² or higher.

9. The semiconductor device according to claim 1,

wherein a Cu wire is bonded to the electrode pad.

10. A semiconductor device comprising:

a first insulating film formed on a principal surface of a semiconductor substrate;

an electrode pad and a wire each formed on the first insulating film so that they are separated away from each other, and each formed of an alloy film to which Cu is added in the same layer as each other;

a second insulating film formed on the principal surface of the semiconductor substrate so as to cover the electrode pad and the wire; and

a first opening formed in the second insulating film so as to expose a part of an upper surface of the electrode pad,

wherein a concentration of the Cu added to the alloy film forming the electrode pad is 2 wt % or more, a concentration of the Cu added to the alloy film forming the wire is less than 2 wt %, and a position of the electrode pad is closer to periphery of a semiconductor chip than a position of the wire.

11. The semiconductor device according to claim 10,

wherein the semiconductor chip has a square shape having:

a first side extending in a first direction and a second side extending in a second direction orthogonal to the first direction, and

the electrode pad is arranged in a first region where a region extending from the first side toward inside of the semiconductor chip and having a first distance in the second direction overlaps a region extending from the second side toward the inside of the semiconductor chip and having a second distance in the first direction.

12. The semiconductor device according to claim 11,

wherein the first distance is 5% of a length of the second side or more, and the second distance is 5% of a length of the first side or more.

13. The semiconductor device according to claim 10,

wherein a Cu wire is bonded to the electrode pad.

14. A method of manufacturing a semiconductor device comprising the steps of:

(a) forming a first insulating film on a principal surface of a semiconductor substrate;

(b) on the first insulating film, sequentially forming a first barrier metal film, a first Al—

Cu alloy film to which Cu having a first concentration is added, and a second barrier metal film;

(c) processing the first barrier metal film, the first Al—

Cu alloy film, and the second barrier metal film so as to form an electrode pad and a wire each formed of the first barrier metal film, the first Al—

Cu alloy film, and the second barrier metal film so that the electrode pad and the wire are separated away from each other;

(d) forming a second insulating film on the principal surface of the semiconductor substrate so as to cover the electrode pad and the wire;

(e) forming, in the second insulating film, a first opening from which the second barrier metal film is exposed, by removing the second insulating film on the electrode pad, and besides, exposing a part of an upper surface of the first Al—

Cu alloy film forming the electrode pad from the first opening by removing the second barrier metal film exposed from the first opening;

(f) forming a Cu film on the exposed part of the upper surface of the first Al—

Cu alloy film forming the electrode pad by an electroless plating method; and

(g) forming a second Al—

Cu alloy film to which Cu having a second concentration higher than the first concentration is added by diffusing the Cu by a heat treatment from the Cu film to the first Al—

Cu alloy film forming the electrode pad.

15. The method of manufacturing the semiconductor device according to claim 14,

wherein the concentration of the Cu of the first Al—

Cu alloy film is less than 2 wt %, and the concentration of the Cu of the second Al—

Cu alloy film is 2 wt % or more.

16. The method of manufacturing the semiconductor device according to claim 14,

wherein Knoop hardness of the second Al—

Cu alloy film is 3 kg/mm² or higher.

17. The method of manufacturing the semiconductor device according to claim 14, further comprising the steps of:

after the step of (g),

(h) forming a plating film on an upper surface of the second Al—

Cu alloy film forming the electrode pad by an electroless plating method; and

(i) forming a plating adhesion film on a surface of the plating film by an electroless plating method.

18. The method of manufacturing the semiconductor device according to claim 17,

wherein the plating film is formed of a Ni film, a Ti film, a Cr film, or a stacked film formed by stacking any of them, and the plating adhesion film is formed of a Pd film, a Au film, or a stacked film formed by stacking the Pd film and the Au film.

19. The method of manufacturing the semiconductor device according to claim 14, further comprising the steps of:

after the step of (g),

(h) coating the second insulating film with a resin, and then, forming a second opening larger than the first opening in the resin so as to overlap the first opening;

(i) forming a plating electrode film connected to the second Al—

Cu alloy film on the resin including inner walls of the first opening and the second opening;

(j) coating the plating electrode film with a resist film, and then, forming a third opening larger than the first opening in the resist film so as to overlap the first opening;

(k) forming a plating film on an upper surface of the plating electrode film exposed from bottom of the third opening by an electroless plating method;

(l) forming a plating adhesion film on a surface of the plating film by an electroless plating method;

(m) removing the resist film; and

(n) removing the exposed plating electrode film.

20. The method of manufacturing the semiconductor device according to claim 19,

wherein the plating film is formed of a Ni film, a Ti film, a Cr film, or a stacked film formed by stacking any of them, the plating adhesion film is formed of a Pd film, a Au film, or a stacked film formed by stacking the Pd film and the Au film, and the plating electrode film is formed of a Ti film, a Pd film, a Cr film, a Cu film, or a stacked film formed by stacking any of them.