FLIP-FLOP CIRCUIT WITH RESISTIVE POLY ROUTING
First Claim
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1. A latch circuit, comprising:
- a tri-state gate having an input, an output, and receiving complementary control signals;
a reverse tri-state gate having an input, an output, and sharing the complementary control signals with the tri-state gate, wherein the reverse tri-state gate is configured to lock an output of the tri-state gate when the tri-state gate is shut-off;
a first undoped polysilicon strip for generating one of the complementary control signals; and
a second undoped polysilicon strip coupled between the output of the tri-state gate and the input of reverse tri-state gate.
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Abstract
A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
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Citations
9 Claims
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1. A latch circuit, comprising:
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a tri-state gate having an input, an output, and receiving complementary control signals; a reverse tri-state gate having an input, an output, and sharing the complementary control signals with the tri-state gate, wherein the reverse tri-state gate is configured to lock an output of the tri-state gate when the tri-state gate is shut-off; a first undoped polysilicon strip for generating one of the complementary control signals; and a second undoped polysilicon strip coupled between the output of the tri-state gate and the input of reverse tri-state gate. - View Dependent Claims (2, 3, 4)
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5. A latch circuit, comprising:
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a tri-state gate having an input, an output, and receiving complementary control signals; a reverse tri-state gate having an input connected to an output of the tri-state gate, an output, and sharing the complementary control signals with the tri-state gate; an inverter connected between the output of the tri-state gate and the output of the reverse tri-state gate, wherein the reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off; a first undoped polysilicon strip that receives a clock signal and generates one of the complementary control signals; and a second undoped polysilicon strip coupled between the output of the tri-state gate and the input of reverse tri-state gate.
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6. A flip-flop circuit, comprising:
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a first latch circuit having; a first tri-state gate having an input, an output and receiving complementary control signals; and a first reverse tri-state gate having an input, an output and sharing the complementary control signals with the first tri-state gate, wherein the first reverse tri-state gate is configured to lock an output of the first tri-state gate when the first tri-state gate is shut-off; and a second latch circuit connected in series with the first latch circuit, the second latch circuit having; a second tri-state gate that shares the complementary control signals with the first tri-state gate, wherein the second tri-state gate is configured to be in an on/off state opposite to the first tri-state gate; and a second reverse tri-state gate that shares the same complementary control signals with the first tri-state gate, wherein the second reverse tri-state gate is configured to lock an output of the second tri-state gate when the second tri-state gate is shut-off, wherein the complementary control signals comprise a first undoped polysilicon strip, and the output of the first reverse tri-state gate is coupled to the output of the first tri-state gate via a second undoped polysilicon strip, and the output of the second reverse tri-state gate is coupled to the output of the second tri-state gate via a third undoped polysilicon strip. - View Dependent Claims (7, 8, 9)
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Specification