SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM

• US 20140286099A1
• Filed: 08/30/2013
• Published: 09/25/2014
• Est. Priority Date: 03/21/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIRAKAWA, Masanobu
• Granted Patent: US 9,136,007 B2
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data.

Claims

1. A semiconductor memory device comprising:

a memory cell array that is capable of storing data in a nonvolatile manner; and

a control section configured to control access to the memory cell array,

wherein the memory cell array stores management data redundantly in a plurality of pages, and

wherein the control section is configured to execute a reading operation on the plurality of pages that store the management data to read the management data.

2. The semiconductor memory device according to claim 1, wherein the memory cell array includes at least first and second string units each including a plurality of memory strings in each of which a plurality of memory cells are connected in series, and the management data is stored redundantly in first and second pages, the first page being located in the first string unit and the second page being located in the second string unit,

3. The semiconductor memory device according to claim 2, wherein the first and second string units share the same plurality of word lines, each of which is commonly connected to one memory cell in each memory string of the first string unit and one memory cell in each memory string of the second string unit.

4. The semiconductor memory device according to claim 3, wherein the first and second pages include memory cells of the first and second string units, respectively, that are connected to the same word line.

5. The semiconductor memory device according to claim 3, wherein the first and second pages include memory cells of the first and second string units, respectively, that are connected to different word lines.

6. The semiconductor memory device according to claim 1, wherein the memory cell array includes a first block of memory cells all of which are erased together during an erasing operation and a second block of memory cells all of which are erased together during an erasing operation, and the management data is stored redundantly in first and second pages, the first page being located in the first block and the second page being located in the second block.

7. The semiconductor memory device according to claim 1,

wherein immediately after electric power is supplied to turn on the semiconductor memory device, the control section reads the management data from the plurality of pages without receiving a read command from the outside.

8. The semiconductor memory device according to claim 1,

wherein the control section is configured to execute a reading operation on the plurality of pages that store the management data at the same time.

9. The semiconductor memory device according to claim 1, wherein the control section is configured to execute a reading operation on the plurality of pages that store the management data at different times.

10. A controller that controls the semiconductor memory device having a first block of memory cells all of which are erased together during an erasing operation and a second block of memory cells all of which are erased together during an erasing operation, comprising:

a first control section configured to control access to the memory cell array;

a second control section configured to read defect information of the memory cells in the semiconductor memory device; and

an internal memory that retains the defect information,

wherein the second control section is configured to write data redundantly in a plurality of pages according to the defect information.

11. The controller according to claim 10, wherein the defect information is generated per block and the defect information for a particular block is based on the number of memory hole opening defects in the memory cells of said particular block.

12. The controller according to claim 11, wherein the internal memory indicates blocks with a low number of memory hole opening defects and blocks with a high number of memory hole opening defects, and wherein for blocks with the low number of memory hole opening defects, data is not redundantly written, and for blocks with the high number of memory hole opening defects, data is redundantly written.

13. The controller according to claim 10, wherein the data written is user data.

14. The controller according to claim 10, wherein the data written is management data.

15. A method of accessing management data of a semiconductor memory device having a memory cell array that is capable of storing data in a nonvolatile manner and a control section configured to control access to the memory cell array, said method comprising:

upon power on, executing a reading operation on the plurality of pages that redundantly store management data to read the management data; and

storing the management data in a register.

16. The method according to claim 15, wherein the memory cell array includes at least first and second string units each including a plurality of memory strings in each of which a plurality of memory cells are connected in series, and the management data is stored redundantly in first and second pages, the first page being located in the first string unit and the second page being located in the second string unit,

17. The method according to claim 16, wherein the first and second string units share the same plurality of word lines, each of which is commonly connected to one memory cell in each memory string of the first string unit and one memory cell in each memory string of the second string unit.

18. The method according to claim 17, wherein the first and second pages include memory cells of the first and second string units, respectively, that are connected to the same word line.

19. The semiconductor memory device according to claim 18, wherein the reading operation is executed on the plurality of pages that store the management data at the same time.

20. The semiconductor memory device according to claim 18, wherein the reading operation is executed on the plurality of pages that store the management data at different times.