PROCESSING UNIT AND ERROR PROCESSING METHOD

• US 20140289556A1
• Filed: 03/06/2014
• Published: 09/25/2014
• Est. Priority Date: 03/25/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MIYAMORI, Takashi, SANO, Toru
• Granted Patent: US 9,256,495 B2
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/141 for bus or memory accesses

Abstract

A processing unit of the embodiments includes an instruction memory that holds a plurality of instructions specified by addresses, and that cannot execute read and write operations concurrently, an error correction circuit that detects and corrects an error in the instruction, a program counter, an instruction buffer that holds the instruction corrected as a corrected instruction, a program counter buffer that holds an address of the instruction where an error has been detected, a selector that selects and outputs any of the output of the error correction circuit and the output of the instruction buffer, and a control unit that controls the read and write of the instruction specified by the address from and into the instruction memory. The control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer when a predetermined condition is satisfied after the occurrence of the error.

Claims

1. A processing unit comprising:

an instruction memory configured to hold a plurality of instructions specified by addresses, and to unexecute read and write operations concurrently;

an error correction circuit configured to detect and correct an error in the instruction read from the instruction memory;

a program counter configured to specify the address of instruction memory;

an instruction buffer configured to hold the instruction corrected by the error correction circuit as a corrected instruction;

a program counter buffer configured to hold an address of the instruction where an error has been detected in the error correction circuit;

a selector configured to select and output one of an output of the error correction circuit and an output of the instruction buffer; and

a control unit configured to control read and write of the instruction specified by the address from and into the instruction memory,

wherein the control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer upon a predetermined condition being satisfied after occurrence of a first error.

2. The processing unit according to claim 1, wherein the control unit writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon the program counter specifying the address held in the program counter buffer after the occurrence of the first error.

3. The processing unit according to claim 2, wherein the control unit causes the selector to select the output of the instruction buffer upon the program counter specifying an address held in the program counter buffer after the occurrence of the first error.

4. The processing unit according to claim 1, wherein the control unit writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

5. The processing unit according to claim 2, wherein the control unit writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

6. The processing unit according to claim 3, wherein the control unit writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

7. The processing unit according to claim 1, further comprising a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer, wherein the control unit activates the valid register upon the occurrence of the first error, and writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

8. The processing unit according to claim 2, further comprising a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer, wherein the control unit activates the valid register upon the occurrence of the first error, and writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

9. The processing unit according to claim 4, further comprising a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer, wherein the control unit activates the valid register upon the occurrence of the first error, and writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

10. The processing unit according to claim 5, further comprising a valid register configured to hold as a state whether or not to be in a valid. state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer, wherein the control unit activates the valid register upon the occurrence of the first error, and writes the corrected instruction in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

11. An error processing method in a processing unit including:

an instruction memory configured to hold a plurality of instructions specified by addresses, and to unexecute read and write operations concurrently;

an error correction circuit configured to detect and correct an error in the instruction read from the instruction memory;

a program counter configured to specify the address of instruction memory;

an instruction buffer configured to hold the instruction corrected by the error correction circuit as a corrected instruction;

a program counter buffer configured to hold an address of the instruction where an error has been detected in the error correction circuit;

a selector configured to select and output one of an output of the error correction circuit and an output of the instruction buffer; and

a control unit configured to control read and write of the instruction specified by the address from and into the instruction memory,

the method comprising writing the corrected instruction in the instruction memory using an address held. in the program counter buffer upon a predetermined condition being satisfied after occurrence of a first error.

12. The error processing method according to claim 11, wherein the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon the program counter specifying the address held in the program counter buffer after the occurrence of the first error.

13. The error processing method according to claim 12, wherein the selector is caused to select the output of the instruction buffer upon the program counter specifying an address held in the program counter buffer after the occurrence of the first error.

14. The error processing method according to claim 11, wherein the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

15. The error processing method according to claim 12, wherein the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

16. The error processing method according to claim 13, wherein the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon occurrence of a second error after the occurrence of the first error.

17. The error processing method according to claim 11, wherein

the processing unit further includes a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer,

the valid register is activated upon the occurrence of the first error, and

the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon the valid. register being valid.

18. The error processing method according to claim 12, wherein

the processing unit further includes a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer,

the valid register is activated upon the occurrence of the first error, and

the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

19. The error processing method according to claim 14, wherein

the processing unit further includes a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer,

the valid register is activated upon the occurrence of the first error, and

the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon the valid register being valid.

20. The error processing method according to claim 15, wherein

the processing unit further includes a valid register configured to hold as a state whether or not to be in a valid state where an address of the instruction where an error has been detected in the error correction circuit is stored in the program counter buffer,

the valid register is activated upon the occurrence of the first error, and

the corrected instruction is written in an address held in the program counter buffer of the instruction memory upon the valid register being valid.