MEMORY SYSTEM

• US 20140289588A1
• Filed: 06/04/2014
• Published: 09/25/2014
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAGADOMI, Yasushi, Takashima, Daisaburo, Hatsuda, Kosuke
• Granted Patent: US 9,075,740 B2
• Time in Patent Office: Days
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.

Claims

1-14. -14. (canceled)

15. A memory system comprising:

a nonvolatile memory comprising a plurality of storage areas each including memory portions that each store one of a first data item and a second data item;

a cache memory that temporarily stores data read from the nonvolatile memory;

a control circuit that controls the nonvolatile memory and the cache memory; and

an interface circuit that communicates with a host,

wherein the control circuit is configured to execute;

a first determination in which it is determined whether data is written in each of the storage areas, counting a number of first data items stored in the memory portions in each of the storage areas; and

a second determination in which the storage areas are sequentially read to determine a boundary between a first storage area in which data is written and a second storage area in which data is not written.

16. The memory system according to claim 15, wherein the control circuit comprises a counter that is configured to count the number of the first data items.

17. The memory system according to claim 15, wherein when the second data is stored in all of the memory portions in one of the storage areas, the control circuit is configured to determine that the one of the storage areas is the second storage area with no data.

18. The memory system according to claim 15, wherein when the first data item is stored in at least one of the memory portions in one of the storage areas, the control circuit is configured to determine that the one of the storage areas is the first storage area in which data is written.

19. The memory system according to claim 15, wherein addresses are assigned to the respective storage areas, and the control circuit is configured to read the storage areas in an order of address.

20. The memory system according to claim 15, wherein when executing the first determination, the control circuit is configured to acquire an address assigned to the second storage area without transferring, to the cache memory, the data read from the nonvolatile memory.

21. The memory system according to claim 15, wherein the control circuit is configured to set a variable determination criterion in association with the first determination.

22. The memory system according to claim 15, wherein

the control circuit comprises an ECC module, the ECC module being configured to generate an ECC code including the first data item, and to add, when the second data item is stored in all of the memory portions of one of the storage areas, the ECC code to the one of the storage areas;

and

when executing the first determination, the control circuit is configured to use, as a determination condition for the first determination, whether data read from the nonvolatile memory contains an ECC error.

23. The memory system according to claim 15, wherein

the control circuit has a function of adding an identification number including the first data item to each of the storage areas;

and

when executing the first determination, the control circuit is configured to use, as a determination condition for the first determination, whether the identification number is added to data read from the nonvolatile memory.

24. The memory system according to claim 15, wherein the control circuit is configured to use a number of times of sequential detection of the second storage area as a determination condition for the first determination.