SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20140291756A1
• Filed: 02/12/2014
• Published: 10/02/2014
• Est. Priority Date: 03/26/2013
• Status: Active Grant

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Oka, Toru
• Granted Patent: US 9,349,856 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.

Claims

1. A semiconductor device comprising:

a first n-type semiconductor layer that includes a first interface and a second interface, wherein the second interface forms an upper surface of a convex protruded from the first interface;

a p-type semiconductor layer that is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface, wherein the first region is uniformly continuous with the second region;

a second n-type semiconductor layer that is stacked on the p-type semiconductor layer; and

a trench that is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.

2. The semiconductor device according to claim 1, wherein

the p-type semiconductor layer includes a first projection that is protruded along the convex toward a protruding direction in which the convex is protruded,

the second n-type semiconductor layer includes a second projection protruded along the first projection toward the protruding direction.

3. The semiconductor device according to claim 1, further comprising an electrode that is formed in the trench via an insulating film.

4. The semiconductor device according to claim 1, wherein a height Hm of the convex protruded from the first interface is less than a total thickness Tu obtained by adding a thickness Tp of the p-type semiconductor layer in the first region and a thickness Tn of the second n-type semiconductor layer on the first region.

5. The semiconductor device according to claim 1, wherein a depth h1 by which the trench is depressed into the upper surface of the convex is not less than 0.0 μ

m and is not greater than a total depth obtained by adding the height Hm of the convex protruded from the first interface and 0.4 μ

m.

6. The semiconductor device according to claim 1, wherein a height h2 from the first interface to a bottom face of the trench along an X-axis direction in which the convex is protruded is not greater than 1.0 μ

m on a +X-axis direction side from the first interface toward the second interface, and is not greater than 0.4 μ

m on a −

X-axis direction side from the second interface toward the first interface.

7. The semiconductor device according to claim 1, wherein a distance w1 between a lateral end of the convex and a bottom face of the trench satisfies 0.1 μ

m≦

w1≦

2.0 μ

m.

8. The semiconductor device according to claim 1, wherein a distance w1 between a lateral end of the convex and a bottom face of the trench satisfies 0.2 μ

m≦

w1≦

1.0 μ

m.

9. The semiconductor device according to claim 1, further comprising a third n-type semiconductor layer that is placed between the first n-type semiconductor layer and the p-type semiconductor layer.

10. The semiconductor device according to claim 1, further comprising an intrinsic semiconductor layer that is placed between the first n-type semiconductor layer and the p-type semiconductor layer.

11. The semiconductor device according to claim 1, wherein an acceptor concentration in the first region is equal to an acceptor concentration in the second region.

12. The semiconductor device according to claim 1, wherein the first n-type semiconductor layer, the p-type semiconductor layer and the second n-type semiconductor layer are semiconductor layers mainly made of gallium nitride (GaN).

13. The semiconductor device according to claim 1, wherein there are a plurality of the trenches, and the convex is protruded from the first interface at least on a terminal side of an end trench located on the terminal side of the semiconductor device among the plurality of trenches.

14. The semiconductor device according to claim 1, further comprising:

a step portion that is formed on a terminal side of the trench in the semiconductor device and extended from the second n-type semiconductor layer through the p-type semiconductor layer to the first n-type semiconductor layer;

an insulating film that is configured to have electrical insulation and cover the step portion; and

an electrode that is configured to have electrical conductivity and stacked on the insulating film such that the insulating film is placed between the electrode and the step portion.

15. The semiconductor device according to claim 1, further comprising:

a source electrode that is formed in a recess from the second n-type semiconductor layer to the p-type semiconductor layer; and

a gate electrode that is formed in the trench via an insulating film,

wherein parts of the source electrode and parts of the gate electrode are arranged alternately in a cross section along a stacking direction in which the first n-type semiconductor layer, the p-type semiconductor layer and the second n-type semiconductor layer are stacked.

16. The semiconductor device according to claim 1,

wherein the first n-type semiconductor layer includes:

an n-type semiconductor layer on a lower layer side away from the p-type semiconductor layer; and

an n-type semiconductor layer on an upper layer side having the first interface and the second interface,

wherein another convex having another upper surface is formed at a location corresponding to the convex on the n-type semiconductor layer on the lower layer side, another p-type semiconductor layer different from the p-type semiconductor layer is stacked on the another upper surface of the another convex, and the trench is depressed to the another p-type semiconductor layer.

17. The semiconductor device according to claim 16, the trench is in a shape having a bottom face depressed into the another p-type semiconductor layer or in a shape having a bottom face wider than the another p-type semiconductor layer.

18. The semiconductor device according to claim 16, wherein the first n-type semiconductor layer further includes another semiconductor layer that is placed between the n-type semiconductor layer on the lower layer side with the another p-type semiconductor layer and the n-type semiconductor layer on the upper layer side.

19. A manufacturing method of a semiconductor device, the manufacturing method comprising:

forming a first n-type semiconductor layer;

forming a convex in the first n-type semiconductor layer by dry etching;

forming a p-type semiconductor layer on a surface of the first n-type semiconductor layer including the convex by crystal growth;

forming a second n-type semiconductor layer on a surface of the p-type semiconductor layer by crystal growth; and

forming by dry etching a trench depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.

20. The manufacturing method according to claim 19, wherein the forming the convex includes wet etching of the first n-type semiconductor layer after the dry etching.