DRIVER IC AND DISPLAY DEVICE

• US 20140292688A1
• Filed: 03/16/2014
• Published: 10/02/2014
• Est. Priority Date: 04/01/2013
• Status: Active Grant

• Current Assignee: Omnivision TDDI Ontario Limited Partnership
• Original Assignee: Renesas SP Drivers Inc. (Synaptics Incorporated)
• Inventors: Munechika, Isao
• Granted Patent: US 9,383,857 B2
• Time in Patent Office: Days
• US Class Current: 345/173
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

The driver IC includes: a control circuit operable to perform control for creating the timing of detection by a touch panel in a non-display drive period during which the action of a drive circuit remains stopped, and for creating a display drive period during which the drive circuit drives the display panel, and the non-display drive period; and a data RAM operable to hold display data of more than one display line, but smaller than one display frame in capacity. The control circuit performs control for alternately creating the display and non-display drive periods by repeating a memory-addressing operation for writing display data supplied from outside into the RAM and reading the display data from the RAM at a speed faster than the writing speed to provide the read data to the drive circuit two or more times in a period of one display frame according to a wraparound method.

Claims

1. A driver IC which controls the activation of a display panel and the detection timing of a touch panel comprising:

a drive circuit operable to activate the display panel in a display drive period;

a control circuit operable to create the detection timing of the touch panel in a non-display drive period during which the action of the drive circuit remains stopped, and to create the display drive period and the non-display drive period; and

a data RAM operable to hold display data of more than one display line, but smaller than one display frame in capacity,

wherein the control circuit performs the control for alternately creating the display drive period and the non-display drive period by repeating a memory-addressing operation for writing display data supplied from outside into the data RAM and reading the display data from the data RAM at a speed faster than the writing speed to provide the read data to the drive circuit two or more times in a period of one display frame according to a wraparound method.

2. The driver IC according to claim 1, wherein the control circuit has a register circuit for rewritably holding touch interval period data for controlling an addressing range of the memory-addressing operation to be repeated according to the wraparound method within a range of a number of display lines comparable to up to a maximum memory capacity of the data RAM.

3. The driver IC according to claim 2, wherein the control circuit handles, as a page, data of a data size of a number of display lines comparable to up to a maximum memory capacity of the data RAM, and

the control circuit has:

a write address counter circuit which creates a page-write address for each page in each cycle of a first frame synchronizing signal from outside, and creates an in-page line-write address for each page; and

a read address counter circuit which creates a page-read address for each page in each cycle of a second frame synchronizing signal for display action, and creates an in-page line-read address for each page, and

the control circuit creates the display drive period and the non-display drive period for each page-read address alternately, creates a line-read address in the display drive period, and stops the creation of the line-read address in the non-display drive period.

4. The driver IC according to claim 3, wherein the control circuit starts to read display data from the data RAM with a timing delayed from a timing of starting to write display data into the data RAM by a predetermined period for each page-write address, and

the read action is ended after the end of the write to each page-write address.

5. The driver IC according to claim 4, wherein the register circuit further rewritably holds touch-detection-start-line-number data for controlling the number of display lines between the start of write to a write address of the top in a page and the start of touch detection, and display-read-start-line-number data for controlling the number of display lines between the position of a display line number decided by the touch-detection-start-line-number data and the start of display read after execution of touch detection, and

the predetermined period is determined by a sum of the touch-detection-start-line-number data and the display-read-start-line-number data.

6. The driver IC according to claim 5, wherein the control circuit has a line counter which counts, for each display frame, display lines in each display line cycle after start of write to a write address of a top of a top page, and

the control circuit makes a judgment on a line number coming from the ouch detection line number data, and a line number coming from the display-read-start-line-number data based on a count value of the line counter.

7. The driver IC according to claim 4, wherein a unit of data access according to a read request to the data RAM is made larger than a unit of data access according to a write request, and

the control circuit has an arbitration circuit which gives priority to the write request on condition that the write request and the read request conflict with each other.

8. The driver IC according to claim 7, wherein the access unit according to the read request is the number of parallel data of one display line, and

the access unit according to the write request is the number of parallel data of bus access.

9. The driver IC according to claim 2, wherein the data RAM has memory banks,

the control circuit reads data from one memory bank while writing the other memory bank, and

the control circuit alternately switches between the memory bank targeted for write and the memory bank targeted for read.

10. The driver IC according to claim 9, wherein the control circuit sets one of the pair of memory banks as a memory bank targeted for write in a first non-display drive period for each display frame, and sets the other memory bank as a memory bank targeted for read in a first display drive period, and

the control circuit switches between the memory bank targeted for write and the memory bank targeted for read at each page switching.

11. The driver IC according to claim 3, wherein the register circuit rewritably holds:

display line cycle data for controlling a display line cycle of the display panel, which is a switching cycle of a display line to be driven; and

display line number data for controlling the number of display lines of the display panel to be driven.

12. The driver IC according to claim 11, wherein the control circuit handles, as a page, data of a data size of a number of display lines comparable to up to a maximum memory capacity of the data RAM,

the control circuit has:

a write address counter circuit which creates a page-write address for each page in each cycle of a first frame synchronizing signal from outside, and creates an in-page line-write address for each page; and

a read address counter circuit which creates a page-read address for each page in each cycle of a second frame synchronizing signal for display action, and creates an in-page line-read address for each page,

the control circuit creates the display drive period and the non-display drive period for each page-read address alternately, creates a line-read address in the display drive period, and stops the creation of the line-read address in the non-display drive period, and

the register circuit further rewritably holds touch-detection-start-line-number data for controlling the number of display lines between the start of write to a write address of the top in a page and the start of touch detection, and display-read-start-line-number data for controlling the number of display lines between the position of a display line number decided by the touch-detection-start-line-number data and the start of display read after execution of touch detection.

13. The driver IC according to claim 11, wherein the data RAM has memory banks,

the control circuit reads data from one memory bank while writing the other memory bank, and

the control circuit alternately switches between the memory bank targeted for write and the memory bank targeted for read,

the register circuit further rewritably holds:

offset-line-number data for controlling an offset from the start of write to a write address at the top in a page by the number of display lines; and

display-read-start-line-number data for controlling the number of display lines between a position of a display line number decided by the offset-line-number data and the start of the subsequent display read, provided that execution of touch detection is started with a display line when a display line number specified by the touch interval period data has been reached.

14. The driver IC according to claim 12, wherein the control circuit has a line counter which counts, for each display frame, display lines in each display line cycle after start of write to a write address of a top of a top page, and

the control circuit makes judgment on the number of lines in a touch interval period coming from the touch interval period data, the number of lines coming from the touch-detection-line-number data, and the number of lines coming from the display-read-start-line-number data based on a count value of the line counter.

18. The driver IC according to 13, wherein the control circuit has a line counter which counts, for each display frame, display lines in each display line cycle after start of write to a write address of a top of a top page, and

the control circuit makes judgment on the number of lines in a touch interval period coming from the touch interval period data, the number of lines coming from the touch-detection-line-number data, and the number of lines coming from the display-read-start-line-number data based on a count value of the line counter.

15. A display device comprising:

a panel module having a display panel and a touch panel incorporated in the display panel; and

a driver IC provided in the panel module and operable to perform the activation control of the display panel and the detection control of the touch panel,

wherein the driver IC has a drive circuit operable to drive the display panel in a display drive period,

a touch panel controller operable to perform the detection control of the touch panel in a non-display drive period during which the action of the drive circuit remains stopped,

a data RAM operable to hold display data of more than one display line, but smaller than one display frame in capacity, and

a control circuit operable to perform the control for alternately creating the display drive period and the non-display drive period by repeating a memory-addressing operation for writing display data supplied from outside into the data RAM and reading the display data from the data RAM at a speed faster than the writing speed to provide the read data to the drive circuit two or more times in a period of one display frame according to a wraparound method, and further arranged so that the display drive period and the non-display drive period are specified within a line number range of numbers of display lines corresponding to no more than a maximum memory capacity of the data RAM.

16. The display device according to claim 15, wherein the control circuit handles, as a page, data of a data size of a number of display lines comparable to up to a maximum memory capacity of the data RAM, and the control circuit has:

a write address counter circuit which creates a page-write address for each page in each cycle of a first frame synchronizing signal from outside, and creates an in-page line-write address for each page; and

a read address counter circuit which creates a page-read address for each page in each cycle of a second frame synchronizing signal for display action, and creates an in-page line-read address for each page, and

the control circuit creates the display drive period and the non-display drive period for each page-read address alternately, creates a line-read address in the display drive period, and stops the creation of the line-read address in the non-display drive period.

17. The display device according to claim 15, wherein the data RAM has memory banks,

the control circuit reads data from one memory bank while writing the other memory bank, and

the control circuit alternately switches between the memory bank targeted for write and the memory bank targeted for read.