SEMICONDUCTOR MEMORY APPARATUS

• US 20140293689A1
• Filed: 06/11/2014
• Published: 10/02/2014
• Est. Priority Date: 03/30/2011
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SONG, Taek Sang, KWON, Dae Han
• Granted Patent: US 8,867,265 B1
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Claims

1. A semiconductor memory apparatus comprising:

a resistive memory cell;

a first data transmission unit configured to control an amount of current for the resistive memory cell according to a voltage level of a selection signal;

a data sensing unit configured to sense a first output voltage formed by a sensing current supplied to the resistive memory cell through the first data transmission unit, based on a reference voltage, and output data having a value corresponding to the sensing result;

a dummy memory cell comprising first and second resistors coupled in parallel to each other and having first and second resistance values, respectively; and

a second data transmission unit configured to control an amount of current for the dummy memory cell according to the voltage level of the selection signal and output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage,

wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current.

2. The semiconductor memory apparatus according to claim 1, wherein the first and second resistors are designed in such a manner as to have the same characteristic by modeling a resistor included in the resistive memory cell.

3. The semiconductor memory apparatus according to claim 1, wherein a resistor included in the resistive memory cell has the first or second resistance value according to a data value stored therein.

4. The semiconductor memory apparatus according to claim 3, wherein the resistor is formed of a phase change material.

5. The semiconductor memory apparatus according to claim 1, wherein the first and second resistors are configured to have the same resistance change amount as a resistor included in the resistive memory cell, according to a PVT variation.