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IMAGE PROCESSING CIRCUIT AND IMAGE DETECTION DEVICE

  • US 20140294293A1
  • Filed: 03/19/2014
  • Published: 10/02/2014
  • Est. Priority Date: 03/29/2013
  • Status: Active Grant
First Claim
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1. An image processing circuit for obtaining a probability value indicative of a probability that an input image is a specific image, said circuit comprising:

  • a first selection circuit for selecting one evaluation value out of a plurality of evaluation values which indicate respective characteristics of a plurality of pixels included in said input image and are allocated with positions different from one another, and outputting the selected value;

    a plurality of second selection circuits, each for selecting one evaluation value from said plurality of evaluation values and outputting the selected value;

    a plurality of storage circuits provided respectively corresponding to said plurality of second selection circuits;

    a plurality of integration circuits provided respectively corresponding to said plurality of second selection circuits;

    an addition circuit; and

    a control circuit for controlling selection of the evaluation values in said first selection circuit and said plurality of second selection circuits,whereinsaid first selection circuit sequentially changes one evaluation value selected out of said plurality of evaluation values, to change an evaluation value to be outputted,each of said plurality of second selection circuits selects, out of said plurality of evaluation values, one evaluation value being in a predetermined relative positional relation with a first evaluation value as an evaluation value which is outputted from said first selection circuit, and outputs the selected value,said predetermined relative positional relations are different from one another among said plurality of second selection circuits,each of said plurality of storage circuits stores a weigh value based on a learning sample concerning said specific image in accordance with a combination of a second evaluation value as an evaluation value which is outputted from the corresponding second selection circuit and said first evaluation value which makes a pair with the second evaluation value and is outputted from said first selection circuit,every time said second evaluation value is outputted from the second selection circuit corresponding to the integration circuit, the integration circuit reads, from the storage circuit corresponding to the second selection circuit, said weigh value in accordance with a combination of the second evaluation value and said first evaluation value which makes a pair with the second evaluation value and is outputted from said first selection circuit, to integrate the read values and outputs the consequently obtained integrated value, andsaid addition circuit at least adds a plurality of integrated values outputted from said plurality of integration circuits, so that an addition value is obtained and becomes said probability value.

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