METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING GROOVED SOURCE CONTACT REGION
First Claim
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1. A method of fabricating a semiconductor device, comprising:
- forming a channel layer on a substrate;
forming trench patterns in the channel layer;
forming impurity bodies in the channel layer between the trench patterns;
forming grooves in the impurity bodies formed in the channel layer;
forming source isolation regions in the impurity bodies at bottom portions of the grooves; and
forming source regions in the impurity bodies at sidewall portions of the grooves.
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Abstract
In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.
12 Citations
20 Claims
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1. A method of fabricating a semiconductor device, comprising:
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forming a channel layer on a substrate; forming trench patterns in the channel layer; forming impurity bodies in the channel layer between the trench patterns; forming grooves in the impurity bodies formed in the channel layer; forming source isolation regions in the impurity bodies at bottom portions of the grooves; and forming source regions in the impurity bodies at sidewall portions of the grooves. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of fabricating a semiconductor device, comprising:
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forming a channel layer including N-type impurity regions on a substrate; forming trenches in the channel layer; forming shield patterns in lower regions of the trenches; forming gate patterns on the shield patterns; forming capping patterns on the gate patterns; forming P-type impurity regions in the channel layer between the capping patterns and between the gate patterns; etching the P-type impurity regions in the channel layer between the capping patterns to form grooves having inclined sidewall portions; and forming N-type source regions in the P-type impurity regions disposed in the channel layer at the inclined side surfaces of the grooves.
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16. A method of fabricating a semiconductor device, comprising:
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forming a plurality of cell trenches in a channel layer; forming cell gates in the cell trenches; forming a groove in the channel layer between neighboring ones of the cell trenches, the groove having a first width at an upper portion thereof and a second width at a lower portion thereof, the first width being greater than the second width; after forming the groove, forming a source isolation region at a bottom portion of the groove; and after forming the groove, forming source regions at opposed sidewalls of the channel layer between the cell trenches, the source regions having a first width at an upper portion thereof and a second width at a lower portion thereof, the second width being greater than the first width. - View Dependent Claims (17, 18, 19, 20)
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Specification