System and method for optimized board test and configuration

• US 20140298125A1
• Filed: 03/29/2013
• Published: 10/02/2014
• Est. Priority Date: 03/29/2013
• Status: Active Grant

• Current Assignee: Gopel Electronic GmbH, Testonica Lab Ou
• Original Assignee: Gopel Electronic GmbH, Testonica Lab Ou
• Inventors: DEVADZE, Sergei, JUTMAN, Artur, ALEKSEJEV, Igor, SHIBIN, Konstantin, WENZEL, Thomas
• Granted Patent: US 9,164,858 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

The present invention, system and method for optimized board test and configuration, comprises a method for splitting test data into dynamic and static parts, a system for optimized test access using variable-length shift register (VLSR) that uses the latter method, a system for optimized test application using VLSR with accumulating buffer (VLSRB) and a method for switching between BS-based test and VLSR/VLSRB-based test.

Claims

1. A system for optimized board test and configuration comprises JTAG (Joint Test Action Group) control system (401) and electronic assembly (402), the electronic assembly (402) comprises programmable logic device (403), it'"'"'s pins (404) and device under test (420) connected to the pins of programmable logic device (403), wherein part of programmable logic device comprises internal JTAG interface (405) which comprises instruction register (406), JTAG scan-cells (408) that are connected with pins of programmable logic device (404), multiplexer (409) and de-multiplexer (410), test data input (TDI) (411), test data output (TDO) (412) and reprogrammable part of programmable logic device (403) comprises Variable-Length Shift Register (VLSR(B)) (430) architecture connected with pins (404), JTAG interface (405) comprises a group of separate scan-chains and VLSR(B) (430) comprises scan-cells (501) connected to pins (404) and form one or more scan-path (510), wherein each or part of cells (501) are supplemented with bypassing circuits (502).

2. The system according to claim 1, wherein each bypassing circuit (502) contains a multiplexing block (503) that is controlled by mask signal (504).

3. The system according to claim 1, wherein each bypassing circuit (502) contains a multiplexing block (503) that is controlled by mask signal (504) and each mask signal (504) is controlled by a separate mask cell (507).

4. The system according to claim 1, wherein each bypassing circuit (502) contains a multiplexing block (503) that is controlled by mask signal (504), each mask signal (504) is controlled by a separate mask cell (507) and mask cells (504) form one or more mask scan-chains (508).

5. The system according to claim 1, wherein each bypassing circuit (502) contains a multiplexing block (503) that is controlled by mask signal (504) and single shared mask cell (706) is used to control mask signal of scan-cell of input/output type and mask signal of scan-cell of control type, provided these scan-cells are connected with the same pin (404).

6. The system according to claim 1, wherein scan-path (510) contains dummy cells (601) that are not connected to any of pins 404.

7. The system according to claim 1, wherein scan-path (510) contains dummy cells (601) that are not connected to any of pins 404 and each or part of dummy cells (601) are accomplished with bypassing circuits (602), mask signals (603) and mask cells (604).

8. The system according to claim 1, wherein scan-cells (501) are grouped into scan-paths according to the types of scan-cells.

9. The system according to claim 1, wherein scan-cells (501) are grouped into scan-paths according to the types of scan-cells and scan-cells are grouped into the following scan-paths:

scan-path (901) that comprises scan-cells of an output type;

scan-path (903) that comprises scan-cells of an input type;

scan-path (905) comprises scan-cells of control type.

10. The system according to claim 1, wherein scan-cells (501) are grouped into scan-paths according to the types of scan-cells and scan-cells are grouped into the following scan-paths:

scan-path (1001) that comprises scan-cells of input/output type;

scan-path (1003) that comprises scan-cells of control type.

11. A system for optimized board test and configuration comprises JTAG (Joint Test Action Group) control system (401) and electronic assembly (402), the electronic assembly (402) comprises programmable logic device (403), it'"'"'s pins (404) and device under test (420) connected to the pins of programmable logic device (403), wherein part of programmable logic device comprises internal JTAG interface (405) which comprises instruction register (406), JTAG scan-cells (408) that are connected with pins of programmable logic device (404), multiplexer (409) and de-multiplexer (410), test data input (TDI) (411), test data output (TDO) (412) and reprogrammable part of programmable logic device (403) comprises Variable-Length Shift Register (VLSR(B)) (430) architecture connected with pins (404), JTAG interface (405) comprises a group of separate scan-chains and VLSR(B) (430) comprises at least one scan-path accomplished with at least one accumulating buffer (1201).

12. The system according to claim 11, wherein VLSR(B) accomplished with comparator (1203) and error signal line (1204).

19. A method for optimized board test and configuration comprises, wherein the test is carried out as a VLSRB-based test using the system according to claim 12 and comprises following steps:

preload of test patterns into the buffer (1201) via test data input (411);

applying the preloaded test patterns from buffer (1201) to DUT (420) while capturing responses of DUT (420) into the buffer (1201);

reading out captured responses of DUT from buffer (1201) via test data output (412).

13. A method for optimized board test and configuration comprises following phases:

a. Splitting test data into static and dynamic parts;

b. Applying static data;

c. Reconfiguring VLSR/VLSRB;

d. Applying dynamic data and reading back the responses of DUT.

14. The method according to claim 13, wherein splitting test data into dynamic and static parts in phase a) comprises following steps:

Identify pins (404) which are connected to DUT (420) and mark corresponded scan-cells (501) as dynamic part;

Marking rest of scan-cells (501) as static part.

15. The method according to claim 13, wherein splitting test data into dynamic and static parts in phase a) comprises following steps:

Analyze test pattern set;

Identify scan-cells (501) in which test data is changing frequently and mark those cells as dynamic part;

Mark the rest of scan-cells as static part.

16. The method according to claim 13, wherein applying static data in phase b) comprises following steps:

Selecting the mask chain (508) as target scan-chain by loading the corresponded instruction into the instruction register (406) of JTAG interface (405) using IR-shift operation;

Configuring mask signals 504 to include all scan-cells (501) into scan-paths by loading mask cells (507) of mask-chain (508) with the corresponded values;

Repeating the previous two steps, if VLSR architecture contains multiple mask registers (508);

Selecting data scan-chain (510) populated with scan-cells (501) by loading the corresponded instruction into the instruction register (406);

Shifting-in static data into the selected chain via test data input (411) using DR-shift operation;

Repeating the previous two steps until all the data scan-chains in VLSR populated with scan-cells (501) are filled-in with the prepared static data.

17. The method according to claim 13, wherein reconfiguring VLSR phase c) comprises following steps:

Selecting target mask register (508) by loading corresponded instruction into instruction register (406);

Preparing VLSR configuration data for selected mask register that sets mask cells to values that will force inclusion of only dynamic scan-cells into active scan-path;

Shifting-in VLSR configuration data into the selected mask register (508) via TDI (411) using DR-shift operation;

Repeated the previous three steps until all the mask registers of VLSR architecture are filled-in with the corresponded VLSR configuration data;

activating VLSR architecture for driving static values to external pins (404) by loading corresponded instruction into instruction register (406).

18. The method according to claim 13, wherein applying dynamic data phase d) comprises following steps:

data scan-chain (510) is selected as a target scan-chain;

the dynamic test data is shifted data cells (501) of data register (510);

the previous two steps are repeating until each data scan-chain (510) in VLSR architecture will contain needed test data values;

After all the corresponded scan-cells (510) will contain dynamic test data, the test data is applied to DUT (420) while DUT responses are captured back into scan-cells (510).

20. The method according to claim 13, wherein the test is carried using a system for optimized board test and configuration which comprises JTAG (Joint Test Action Group) control system and electronic assembly, the electronic assembly comprises programmable logic device, it'"'"'s pins and device under test connected to the pins of programmable logic device, wherein part of programmable logic device comprises internal JTAG interface which comprises instruction register, JTAG scan-cells that are connected with pins of programmable logic device, multiplexer and de-multiplexer, test data input TDI test data output TDO and reprogrammable part of programmable logic device comprises Variable-Length Shift Register (VLSR(B)) architecture connected with pins, JTAG interface comprises a group of separate scan-chains and VLSR(B) comprises at least one scan-path accomplished with at least one accumulating buffer, said method is accomplished with following steps:

preloading patterns of expected responses of DUT (420) into the accumulating buffer (1201) via test data input (411) during preload of test patterns;

comparing the responses of DUT during test application with the expected patterns using built-in comparator (1203) and setting the error signal (1204) in case of mismatch;

reading the state of error signal (1204) after the test is finished to determine whether mismatch was occurred during test pattern application.

21. A method for switching between BS-based test and VLSR(B)-based test comprises following steps:

Loading SAMPLE/PRELOAD instruction into IR (406) of BS-compliant ICs (103) of BUT (402) including devices (403) containing VLSR(B);

Preloading test values (static and dynamic) for BUT (402) into BSR (301) of the device (403) and BSRs of other BS-compliant ICs (103);

Uploading the same test values into scan-paths (510) of VLSR or buffer (1201) of VLSRB while VLSR(B) is disabled;

Switching to BS test mode by loading EXTEST instruction into IRs (406) of BS-compliant ICs (103) including devices (403) that contain VLSR(B);

Activating VLSR(B) (430) and deactivating BSR (301) by loading special instruction into IR (406) of device (403) that contains VLSR(B).