FIELD EFFECT TRANSISTOR

• US 20140299923A1
• Filed: 04/08/2013
• Published: 10/09/2014
• Est. Priority Date: 04/08/2013
• Status: Active Grant

• Current Assignee: Design Express Limited
• Original Assignee: Design Express Limited
• Inventors: CHANG, Chun Yen
• Granted Patent: US 9,136,320 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region, wherein the at least one inclined surface has a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation. The hole mobility and the electron mobility are substantially the same in the channel region having a crystalline orientation off from the (110) crystal orientation.

Claims

1. A field effect transistor, comprising:

a semiconductor substrate having a protrusion with at least one inclined surface, the semiconductor substrate comprising doped regions sandwiching a channel region;

a gate insulator disposed at least on a portion of the inclined surface;

a gate conductor disposed on the gate insulator;

wherein the at least one inclined surface has a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation.

2. The field effect transistor of claim 1, wherein the first crystal orientation is (551) and the second crystal orientation is (100).

3. The field effect transistor of claim 1, wherein the semiconductor substrate has a third crystal orientation of (110).

4. The field effect transistor of claim 1, wherein the included angle ranges from 9 to 10 degrees.

5. The field effect transistor of claim 1, wherein the included angle ranges from 7 to 9 degrees.

6. The field effect transistor of claim 1, wherein the included angle ranges from 5 to 7 degrees.

7. The field effect transistor of claim 1, wherein the gate conductor traverses the protrusion horizontally.

8. The field effect transistor of claim 1, wherein the gate conductor surrounds the protrusion horizontally.

9. The field effect transistor of claim 1, wherein the protrusion has a trapezoid profile.

10. The field effect transistor of claim 1, wherein the protrusion has an inverted trapezoid profile.

11. The field effect transistor of claim 1, wherein the doped regions are disposed at the top of the protrusion and the bottom of the semiconductor substrate.

12. The field effect transistor of claim 1, wherein the gate insulator comprises an inclined portion on the inclined surface and a horizontal portion connected to the inclined portion.

13. The field effect transistor of claim 1, wherein the gate conductor comprises an inclined portion on the inclined surface and a horizontal portion connected to the inclined portion.

14. The field effect transistor of claim 1, wherein the doped regions have different conductivity types.

15. A field effect transistor, comprising:

a fin structure comprising a semiconductor material, wherein the fin structure comprises doped regions sandwiching a channel region;

a gate insulator disposed at least on a portion of the fin structure; and

a gate conductor disposed on the gate insulator;

wherein the fin structure has at least one inclined surface with a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation.

16. The field effect transistor of claim 15, wherein the first crystal orientation is (551) and the second crystal orientation is (100).

17. The field effect transistor of claim 15, further comprising a semiconductor substrate having a third crystal orientation of (110), and the fin structure is disposed on the semiconductor substrate.

18. The field effect transistor of claim 15, wherein the included angle ranges from 9 to 10 degrees.

19. The field effect transistor of claim 15, wherein the included angle ranges from 7 to 9 degrees.

20. The field effect transistor of claim 15, wherein the included angle ranges from 5 to 7 degrees.

21. The field effect transistor of claim 15, wherein the gate conductor traverses the fin structure.

22. The field effect transistor of claim 15, wherein the fin structure has a trapezoid profile.

23. The field effect transistor of claim 15, wherein the fin structure has an inverted trapezoid profile.

24. The field effect transistor of claim 15, wherein the doped regions have different conductivity types.