SEMICONDUCTOR DEVICE AND INTERCONNECT SUBSTRATE
First Claim
1. A semiconductor device comprising a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon,wherein the interconnect substrate comprises:
- a first main surface formed with a plurality of first electrodes connected electrically to the semiconductor chip;
a second main surface opposing the first main surface; and
an interconnect region interposed between the first main surface and the second main surface,wherein the first electrodes includes a plurality of first signal electrodes and second signal electrodes arranged orderly for receiving supply of signals each at a predetermined frequency, andwherein the first signal electrodes and the second signal electrodes are disposed being dispersed in the arrangement thereof, andwherein the interconnect region includes;
a core substrate;
a plurality of interconnect layers formed on both surfaces of the core substrate respectively;
a plurality of first through holes that pass through the core substrate for forming impedance matching capacitance;
a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface for forming impedance matching capacitances;
a plurality of first signal interconnects connected to the corresponding first signal electrodes; and
a plurality of second signal interconnects connected to the corresponding second signal electrodes,wherein each first through hole is connected to the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, andwherein the first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.
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Accused Products
Abstract
A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.
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Citations
20 Claims
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1. A semiconductor device comprising a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon,
wherein the interconnect substrate comprises: -
a first main surface formed with a plurality of first electrodes connected electrically to the semiconductor chip; a second main surface opposing the first main surface; and an interconnect region interposed between the first main surface and the second main surface, wherein the first electrodes includes a plurality of first signal electrodes and second signal electrodes arranged orderly for receiving supply of signals each at a predetermined frequency, and wherein the first signal electrodes and the second signal electrodes are disposed being dispersed in the arrangement thereof, and wherein the interconnect region includes; a core substrate; a plurality of interconnect layers formed on both surfaces of the core substrate respectively; a plurality of first through holes that pass through the core substrate for forming impedance matching capacitance; a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface for forming impedance matching capacitances; a plurality of first signal interconnects connected to the corresponding first signal electrodes; and a plurality of second signal interconnects connected to the corresponding second signal electrodes, wherein each first through hole is connected to the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, and wherein the first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An interconnect substrate comprising:
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a main surface formed with a plurality of first electrodes for electric connection with a semiconductor chip; a second main surface opposing the first main surface; and an interconnect region interposed between the first main surface and the second main surface, wherein a first electrode includes a plurality of first signal electrodes and second signal electrodes arranged orderly for receiving supply of signals at a predetermined frequency, wherein the first signal electrode and the second signal electrode are disposed being dispersed in the arrangement thereof, wherein the interconnect region includes; a core substrate; a plurality of interconnect layers formed respectively on both surfaces of the core substrate; a plurality of first through holes that pass through the core substrate for forming impedance matching capacitances; a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface for forming impedance matching capacitances; a plurality of first signal interconnects connected to the corresponding first signal electrodes; and wherein a plurality of second signal interconnects connected to the corresponding second signal electrodes, wherein each first through hole is connected to the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, and wherein the first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length. - View Dependent Claims (19)
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20. A semiconductor device comprising:
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a semiconductor chip; and an interconnect substrate having the semiconductor chip mounted thereon, wherein the interconnect substrate includes; a first main surface electrically connected with the semiconductor chip and formed with a plurality of signal electrodes supplied with signals at a predetermined frequency; a second main surface opposing the first main surface; and an interconnect region interposed between the first main surface and the second main surface, wherein the interconnect region includes; a core substrate; a plurality of interconnect layers formed respectively on both surfaces of the core substrate; a plurality of signal interconnects formed in the interconnect layer and extended from the signal electrodes; and a plurality of impedance matching circuits connected to the signal interconnect each at a position spaced apart from the signal electrode by a predetermined interconnect length, wherein a portion of the plurality of impedance matching circuits is formed of a plurality of through holes that pass through the core substrate and a remaining portion thereof is formed of a plurality of vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface.
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Specification