SEMICONDUCTOR DEVICE AND INTERCONNECT SUBSTRATE

• US 20140300003A1
• Filed: 04/01/2014
• Published: 10/09/2014
• Est. Priority Date: 04/09/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KARIYAZAKI, SHUUICHI, OIKAWA, RYUICHI
• Granted Patent: US 9,035,450 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73153 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.

Claims

1. A semiconductor device comprising a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon,

wherein the interconnect substrate comprises:

a first main surface formed with a plurality of first electrodes connected electrically to the semiconductor chip;

a second main surface opposing the first main surface; and

an interconnect region interposed between the first main surface and the second main surface,

wherein the first electrodes includes a plurality of first signal electrodes and second signal electrodes arranged orderly for receiving supply of signals each at a predetermined frequency, and

wherein the first signal electrodes and the second signal electrodes are disposed being dispersed in the arrangement thereof, and

wherein the interconnect region includes;

a core substrate;

a plurality of interconnect layers formed on both surfaces of the core substrate respectively;

a plurality of first through holes that pass through the core substrate for forming impedance matching capacitance;

a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface for forming impedance matching capacitances;

a plurality of first signal interconnects connected to the corresponding first signal electrodes; and

a plurality of second signal interconnects connected to the corresponding second signal electrodes,

wherein each first through hole is connected to the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, and

wherein the first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.

2. The semiconductor device according to claim 1,

wherein the interconnect region further includes:

a plurality of second through holes passing through the core substrate for forming impedance matching capacitances; and

a plurality of second vias passing through the interconnect layer formed to the core substrate on the side of the second main surface for forming the impedance matching capacitances,

wherein each second through hole is connected with the second signal interconnect at a position spaced apart from the second signal electrode by a third interconnect length longer than the first interconnect length, and

wherein each second via is connected with the first signal interconnect at a position spaced apart from the first signal electrode by a fourth interconnect length that is substantially equal with the third interconnect length.

3. The semiconductor device according to claim 2, wherein

the first interconnect length is a length corresponding to ¼

of an electromagnetic wavelength in accordance with a first frequency in a signal band required for a transmission line of the signal.

4. The semiconductor device according to claim 3, wherein

the third interconnect length is a length corresponding to ¾

of an electromagnetic wavelength in accordance with a second frequency that is different from the first frequency in a signal band required for the transmission line of the signal.

5. The semiconductor device according to claim 2, wherein

the first interconnect length is a length corresponding to ¾

of the electromagnetic wavelength corresponding to the first frequency in a signal band required for the transmission line of the signal.

6. The semiconductor device according to claim 2, wherein

the first through hole and the first via do not overlap in a plan view.

7. The semiconductor device according to claim 2, wherein

the first signal interconnect is a first differential interconnect pair formed by two interconnects in parallel and the second signal interconnect is a second differential interconnect pair formed by two interconnects in parallel.

8. The semiconductor device according to claim 2, wherein

one of the first signal electrode and the second electrode is a receiving electrode for inputting a signal to the semiconductor chip and the other of them is a transmitting electrode for outputting a signal from the semiconductor chip.

9. The semiconductor device according to claim 2, wherein

the diameter of the uppermost land and the diameter of the lowermost land connected to the first through hole are different in a cross sectional view.

10. The semiconductor device according to claim 2, wherein

the first through hole is connected with a plurality of lands in a vertical direction in a cross sectional view.

11. The semiconductor device according to claim 2, wherein

the diameter of the uppermost land and the diameter of the lowermost land connected to the first via are different in a cross sectional view.

12. The semiconductor device according to claim 2, wherein

a plurality of lands are connected in a vertical direction to the first via in a cross sectional view.

13. The semiconductor device according to claim 2, wherein

a portion of a plurality of the first vias is connected by way of one land to the second signal interconnect and a remaining portion of them is connected to the second signal interconnect by way of a plurality of lands.

14. The semiconductor device according to claim 2, wherein

the diameter of the land for the first via is larger than that for the second via.

15. The semiconductor device according to claim 2, wherein

the first via has a larger land diameter than that of the adjacent via for connecting adjacent interconnect layers to each other.

16. The semiconductor device according to claim 2, wherein

the semiconductor chip has a plurality of interface buffers connected being corresponded respectively to the first signal terminal and second signal terminal.

17. A semiconductor device according to claim 16, further comprising:

a plurality of external terminals,

wherein the second main surface comprises a plurality of second electrodes connected electrically to the corresponding external terminals,

wherein the first signal interconnect forms a transmission line electrically connecting the first signal electrode and the corresponding second electrode, and

wherein the second signal interconnect forms a transmission line electrically connecting the second signal electrode and the corresponding second electrode.

18. An interconnect substrate comprising:

a main surface formed with a plurality of first electrodes for electric connection with a semiconductor chip;

a second main surface opposing the first main surface; and

an interconnect region interposed between the first main surface and the second main surface,

wherein a first electrode includes a plurality of first signal electrodes and second signal electrodes arranged orderly for receiving supply of signals at a predetermined frequency,

wherein the first signal electrode and the second signal electrode are disposed being dispersed in the arrangement thereof,

wherein the interconnect region includes;

a core substrate;

a plurality of interconnect layers formed respectively on both surfaces of the core substrate;

a plurality of first through holes that pass through the core substrate for forming impedance matching capacitances;

a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface for forming impedance matching capacitances;

a plurality of first signal interconnects connected to the corresponding first signal electrodes; and

wherein a plurality of second signal interconnects connected to the corresponding second signal electrodes,

wherein each first through hole is connected to the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, and

wherein the first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.

19. The interconnect substrate according to claim 18,

wherein the interconnect region further includes:

a plurality of second through holes that pass through the core substrate for forming impedance matching capacitances; and

a plurality of second vias that pass through the interconnect layer formed to the core substrate on the side of the second main surface for forming impedance matching capacitances,

wherein each second through hole is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a third interconnect length longer than the first interconnect length, and

wherein each second via is connected to the second signal interconnect at a position spaced apart from the first signal electrode by a fourth interconnect length that is substantially equal with the third interconnect length.

20. A semiconductor device comprising:

a semiconductor chip; and

an interconnect substrate having the semiconductor chip mounted thereon,

wherein the interconnect substrate includes;

a first main surface electrically connected with the semiconductor chip and formed with a plurality of signal electrodes supplied with signals at a predetermined frequency;

a second main surface opposing the first main surface; and

an interconnect region interposed between the first main surface and the second main surface,

wherein the interconnect region includes;

a core substrate;

a plurality of interconnect layers formed respectively on both surfaces of the core substrate;

a plurality of signal interconnects formed in the interconnect layer and extended from the signal electrodes; and

a plurality of impedance matching circuits connected to the signal interconnect each at a position spaced apart from the signal electrode by a predetermined interconnect length,

wherein a portion of the plurality of impedance matching circuits is formed of a plurality of through holes that pass through the core substrate and a remaining portion thereof is formed of a plurality of vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface.