Method for Reducing Forming Voltage in Resistive Random Access Memory

• US 20140302659A1
• Filed: 06/23/2014
• Published: 10/09/2014
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: Intermolecular Incorporated
• Original Assignee: Intermolecular Incorporated
• Inventors: Phatak, Prashant B., Kuse, Ronald J., Tong, Jinhong
• Granted Patent: US 9,761,800 B2
• Time in Patent Office: Days
• US Class Current: 438/382
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/041 Modification of switching materials after formation, e.g. doping shaping H10N70/061
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

Claims

1. A method comprising:

depositing a first electrode,

wherein the first electrode comprises polysilicon;

depositing a first resistive switching film over the first electrode,

wherein the first resistive switching film comprises a first dielectric material configured to develop conductive pathways during application of a predetermined voltage and further configured to maintain said conductive pathways after said predetermined voltage is removed,

wherein the first dielectric material comprises oxygen,

wherein the first resistive switching film is deposited at a temperature of less than 200°

C.; and

depositing a second electrode.

2. The method of claim 1, wherein the first dielectric material comprises hafnium oxide.

3. The method of claim 1, wherein the first resistive switching film is deposited using atomic layer deposition (ALD).

4. The method of claim 1, further comprising depositing a second resistive switching film onto the first resistive switching film prior to depositing the second electrode, wherein the first resistive switching layer and the second resistive switching layer form a stack, the stack being configured to develop conductive pathways during application of a predetermined voltage and further configured to maintain said conductive pathways after said predetermined voltage is removed.

5. The method of claim 4, wherein the second resistive switching film is deposited using atomic layer deposition (ALD).

6. The method of claim 4, wherein the second resistive switching film comprises titanium oxide.

7. The method of claim 6, wherein the first resistive switching film comprises hafnium oxide.

8. The method of claim 7, wherein the second electrode comprises titanium nitride.

9. The method of claim 4, further comprising annealing the stack, wherein during annealing the first dielectric material diffuses into the second resistive switching film.

10. The method of claim 9, wherein the annealing is performed prior to depositing the second electrode.

11. The method of claim 1, wherein the first resistive switching film directly interfaces the first electrode.

12. The method of claim 1, prior to forming the first resistive switching film, depositing an additional layer over the first electrode such that the additional layer is disposed between the first electrode and the first resistive switching film.

13. The method of claim 12, wherein the additional layer is formed using physical vapor deposition.

14. The method of claim 13, wherein the additional layer comprises hafnium oxide.

15. The method of claim 12, wherein the additional layer comprises one or more of titanium nickel, cobalt, palladium, or platinum.

16. The method of claim 15, further comprising, prior to forming the first resistive switching film, annealing the additional layer disposed over the first electrode thereby converting a material of the additional layer into silicide.

17. The method of claim 1, wherein the first resistive switching film is deposited using tetrakisdimethylaminohafnium (TDMAH), and wherein the TDMAH is maintained at a temperature between 40°

C. and 50°

C.

18. The method of claim 17, wherein the first resistive switching film is deposited using an oxidizer, and wherein the oxidizer is maintained below room temperature.

19. The method of claim 18, wherein the oxidizer is water.

20. The method of claim 18, wherein the oxidizer is maintained at a temperature of between about 2°

C. and 5°

C.